Freescale Semiconductor MC68332 - Page 146

MC68332 QUEUED SERIAL MODULE
USER’S MANUAL 6-23
Changing the value of SCI control bits during a transfer operation may disrupt opera-
tion. Before changing register values, allow the SCI to complete the current transfer,
then disable the receiver and transmitter.
Figure 6-7 SCI Transmitter Block Diagram
68300 SCI TX BLOCK
0 LOOPS WOMS
ILT
PT PE
M
WAKE
TIE
TCIE
RIE
ILIE
TE
RE RWU
SBK
TRANSMITTER
CONTROL LOGIC
PIN BUFFER
AND CONTROL
H
(8)76543210
L
10 (11) - BIT Tx SHIFT REGISTER
MDDR7
MDDR5
TxD
SCDR Tx BUFFER
TRANSFER Tx BUFFER
SHIFT ENABLE
JAM ENABLE
PREAMBLE–JAM 1's
BREAK–JAM 0's
(WRITE-ONLY)
FORCE PIN
DIRECTION
SIZE 8/9
PARITY
GENERATOR
TRANSMITTER
BAUD RATE
CLOCK
TC
TDRE
SCI Rx
REQUESTS
SCI INTERRUPT
REQUEST
FE NF
OR
IDLE RDRF
TC
TDRE
SCSR (STATUS REGISTER)
PF
INTERNAL
DATA BUS
RAF
TIE TCIE
SCCR1 (CONTROL REGISTER 1)
015 15 0
START
STOP
OPEN DRAIN OUTPUT MODE ENABLE
(OUT)
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Freescale Semiconductor, Inc.
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