REGISTER SUMMARY MC68332
D-28 USER’S MANUAL
HMIE — HALTA and MODF Interrupt Enable
0 = HALTA and MODF interrupts disabled
1 = HALTA and MODF interrupts enabled
HALT — Halt
0 = Halt not enabled
1 = Halt enabled
SPIF — QSPI Finished Flag
0 = QSPI not finished
1 = QSPI finished
MODF — Mode Fault Flag
0 = Normal operation
1 = Another SPI node requested to become the network SPI master while the QSPI
was enabled in master mode (SS
input taken low).
HALTA — Halt Acknowledge Flag
0 = QSPI not halted
1 = QSPI halted
CPTQP — Completed Queue Pointer
CPTQP points to the last command executed. It is updated when the current command
is complete. When the first command in a queue is executing, CPTQP contains either
the reset value ($0) or a pointer to the last command completed in the previous queue.
D.4.14 RR[0:F] — Receive Data RAM $YFFD00–$YFFD0E
Data received by the QSPI is stored in this segment. The CPU32 reads this segment
to retrieve data from the QSPI. Data stored in receive RAM is right-justified. Unused
bits in a receive queue entry are set to zero by the QSPI upon completion of the indi-
vidual queue entry. The CPU can access the data using byte, word, or long-word ad-
dressing.
D.4.15 TR[0:F] — Transmit Data RAM $YFFD20–$YFFD3E
Data that is to be transmitted by the QSPI is stored in this segment. The CPU32 nor-
mally writes one word of data into this segment for each queue command to be exe-
cuted.
Information to be transmitted must be written to transmit data RAM in a right-justified
format. The QSPI cannot modify information in the transmit data RAM. The QSPI cop-
ies the information to its data serializer for transmission. Information remains in trans-
mit RAM until overwritten.
Fr
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cale S
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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