REGISTER SUMMARY MC68332
D-34 USER’S MANUAL
CIRL — Channel Interrupt Request Level
This three-bit encoded field specifies the interrupt request level for all channels. Level
seven for this field indicates a nonmaskable interrupt; level zero indicates that all chan-
nel interrupts are disabled.
CIBV — Channel Interrupt Base Vector
The TPU is assigned 16 unique interrupt vector numbers, one vector number for each
channel. The CIBV field specifies the most significant nibble of all 16 TPU channel in-
terrupt vector numbers. The lower nibble of the TPU interrupt vector number is deter-
mined by the channel number on which the interrupt occurs.
D.5.6 CIER — Channel Interrupt Enable Register $YFFE0A
CH[15:0] — Channel Interrupt Enable/Disable
0 = Channel interrupts disabled
1 = Channel interrupts enabled
D.5.7 CFSR0 — Channel Function Select Register 0 $YFFE0C
D.5.8 CFSR1 — Channel Function Select Register 1 $YFFE0E
D.5.9 CFSR2 — Channel Function Select Register 2 $YFFE10
D.5.10 CFSR3 — Channel Function Select Register 3 $YFFE12
CHANNEL[15:0] — Encoded Time Function for each Channel
Encoded four-bit fields in the channel function select registers specify one of 16 time
functions to be executed on the corresponding channel.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH 15 CH 14 CH 13 CH 12 CH 11 CH 10 CH 9 CH 8 CH 7 CH 6 CH 5 CH 4 CH 3 CH 2 CH 1 CH 0
RESET:
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1514131211109876543210
CHANNEL15 CHANNEL14 CHANNEL13 CHANNEL12
RESET:
0 000000000000000
1514131211109876543210
CHANNEL11 CHANNEL10 CHANNEL9 CHANNEL8
RESET:
0 000000000000000
1514131211109876543210
CHANNEL7 CHANNEL6 CHANNEL5 CHANNEL4
RESET:
0 000000000000000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHANNEL3 CHANNEL2 CHANNEL1 CHANNEL0
RESET:
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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