Freescale Semiconductor MC68332 - Page 28

MC68332 OVERVIEW
USER’S MANUAL 3-3
Figure 3-1 MCU Block Diagram
332 BLOCK
PQS5/PCS2
PQS7/TXD
PQS4/PCS1
PQS6/PCS3
CPU 32
QSM
IMB
TPU
PQS0/MISO
PQS1/MOSI
PQS2/SCK
PORT QS
TXD
PCS2
SCK
MISO
MOSI
CONTROL
PCS1
PQS3/PCS0/SS PCS0/SS
RXD
PCS3
BKPT/DSCLK
IFETCH
/DSI
IPIPE/DSO
DSI DSO IPIPE IFETCH BKPT
IRQ[7:1]
ADDR[23:0]
CONTROL
PORT F
PORT C
FC2
FC1
FC0
BG
BR
BGACK
MODCLK
ADDR[23:19]
CLOCK
EBI
CS
[10:0]
BR/CS0
BG/CS1
BGACK/CS2
R/W
RESET
HALT
BERR
CLKOUT
XTAL
EXTAL
CHIP
SELECTS
CSBOOT
ADDR[18:0]
DATA[15:0]DATA[15:0]
QUOT
TEST
FREEZE/QUOT
TSC
CONTROL
TSC
PC0/FC0/CS3
PC1/FC1/CS4
PC2/FC2/CS5
PC3/ADDR19/CS6
PC4/ADDR20/CS7
PC5/ADDR21/CS8
PC6/ADDR22/CS9
ADDR23/CS10
PF7/IRQ7
PF6/IRQ6
PF5/IRQ5
PF4/IRQ4
PF3/IRQ3
PF2/IRQ2
PF1/IRQ1
PF0/MODCLK
CONTROL
PORT E
SIZ1 PE7/SIZ1
SIZ0 PE6/SIZ0
DSACK0
PE0/DSACK0
DSACK1 PE1/DSACK1
AVEC PE2/AVEC
PE3/RMC
DS PE5/DS
RMC
PE4/AS
T2CLK T2CLK
TPUCH[15:0] TPUCH[15:0]
XFC
V
DDSYN
2 KBYTES
RAM
V
STBY
CONTROL
AS
CONTROL
DSCLK
FREEZE
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Freescale Semiconductor, Inc.
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