Intel Agilex Series User Manual

5.4.2.4. Modifying the List of Application Images
The SDM uses the configuration pointer block to determine priority of application images.
The pointer block operates by taking into account the following characteristics of quad SPI flash memory:
• On a sector erase, all the sector flash bits become 1’s.
• A program operation can only turn 1’s into 0’s.
The pointer block contains an array of values which have the following meaning:
• All 1’s – the entry is unused. The client can write a pointer to this entry. This is the state after a quad SPI erase operation
occurs on the pointer block.
• All 0’s – the entry has been previously used and then canceled.
• A combination of 1's and 0's – a valid pointer to an application image.
When the configuration pointer block is erased, all entries are marked as unused. To add an application image to the list, the
client finds the first unused location and writes the application image address to this location. To remove an application image
from the list, the client finds the application image address in the pointer block list and writes all 0's to this address.
If the configuration pointer block runs out of space for new application images, the client compresses the pointer block by
completing the following actions:
1. Read all the valid entries from the configuration
2. Erase the pointer block
3. Add all previously valid entries
4. Add the new image
When using HPS to manage RSU, both the U-Boot and LIBRSU clients implement the block compression. For designs that
drive RSU from FPGA logic, you can implement pointer block compression many different ways, including Nios II code, a
scripting language, or a state machine.
Pointer block compression does not occur frequently because the pointer block has up to 508 available entries.
There are two configuration pointer blocks: a primary (CPB0) and a backup (CPB1). Two blocks enable the list of application
images to be protected if a power failure occurs just after erasing one of them. When a CPB is erased and re-created, the
header is written last. The CPB header is checked prior to use to prevent accidental use if a power failure occurred. For more
information, refer to the Configuration Pointer Block Layout topic. When compressing, the client compresses (erases and
5. Remote System Update (RSU)
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Configuration User Guide
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Intel Agilex Series Specifications

General

Architecture	FPGA
AI Tensor Blocks	Yes
Category	FPGA
Family	Agilex
Transceiver Speed	Up to 112 Gbps
Manufacturer	Intel
Series	Agilex
Transceiver Data Rate	Up to 112 Gbps
Memory Support	HBM2E
PCIe Support	PCIe 5.0
Memory	HBM2e
Power Efficiency	Improved over previous generations
Operating Temperature	Commercial, Industrial
Process Technology	10nm