Intel Agilex Series

Document Version Intel Quartus
Prime Version
Changes
• Revised footnote in the Intel Agilex Configuration Scheme, Data Width, and MSEL table. CvP protocol is not available for
the PCIe Gen3x8 and Gen4x8 in the P-tile device.
• Revised Additional Clock Requirements for HPS and Transceivers. Removed mention of PCIe and HBM2 IP.
• Updated MSEL Settings topic.
— Updated footnote for AS Fast mode. To support this mode, all power supplies must ramp-up to the recommended
operating condition within 10 ms.
—
Added footnote for AS Normal mode. To support the mode, the V
CCIO_SDM
supply must ramp-up to the recommended
operation condition within 10 ms.
— Revised Updating Decision Firmware. Added statement about using a combined application image to update the
decision firmware.
• Restructured PFL II IP content in the Avalon-ST Configuration chapter.
•
Added statement in The AVST_READY Signal. The PFL II IP core includes the AVST_READY synchronizer logic if you use
PFL II IP core as the configuration host.
• Added note in the PFL II IP Functional Description. The PFL II IP does not support HPS cold reset.
• Added new topics:
— Designing with the PFL II IP Core for Avalon-ST Single Device Configuration
— Constraining the PFL II IP Core
— PFL II IP Recommended Design Constraints to FPGA Avalon-ST Pins
— PFL II IP Recommended Design Constraints for Using QSPI Flash
— PFL II IP Recommended Design Constraints for Using CFI Flash
• Added new QSPI flash recommendation for PCIe designs in the AS Configuration Scheme Hardware Components and File
Types section.
• Revised Debugging Guidelines for the AS Configuration Scheme to clarify AS Fast mode ramp-up power supplies
requirement of 10 ms.
• Revised statement in the Including the Reset Release Intel FPGA IP in Your Design chapter regarding holding Reset
Release Intel FPGA IP in reset after configuration is complete. Removed the INIT_DONE signal dependency.
— Removed Assigning INIT_DONE To an SDM_IO Pin.
•
Revised RSU_IMAGE_UPDATE description in the Command List and Description table.
•
Restructured Operation Commands. Removed major and minor error code descriptions for the CONFIG_STATUS and
RSU_STATUS commands. The major and minor error codes are now documented as an appendix in the Mailbox Client Intel
FPGA IP User Guide.
• Added new Use relative address parameter description in the Generating an Application Image section.
— Updated the Specifying Parameters for an Application .rpd Stored in Flash Memory figure to include the new parameter.
• Revised the General Configuration Debugging Checklist table. The SDM debug toolkit is not available for the Intel Agilex
devices.
•
Revised Understanding Configuration Status Using quartus_pgm command. Added quartus_pgm command for clarity.
2020.12.14
20.4 Made the following changes:
continued...
9. Document Revision History for the Intel Agilex Configuration User Guide
683673 | 2021.10.29
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