Intel Agilex Series

Document Version Intel Quartus
Prime Version
Changes
• Revised CvP description in the Intel Agilex Configuration Overview.
• Revised Specifying Boot Order for Intel Agilex SoC Devices topic. Added text stating that FPGA reconfiguration is not
allowed in the FPGA configuration first mode.
• Revised Intel Agilex Configuration Architecture topic. Removed description of specific blocks for Intel Agilex variants.
Referred user to the Device Overview for latest information.
• Revised Additional Clock Requirements for HPS, PCIe, and HBM2 topic.
—
In the FPGA configuration section, removed P-tile specific REFCLK_GXP clock.
— Added text states that the clock frequencies must match the frequency setting specified in the Intel Quartus Prime
software.
• Revised SDM Pin Mapping. Removed text stating that all SDM input signals include Schmitt triggers and all SDM outputs
are open collector.
•
Revised Enabling Dual-Purpose Pins. AVST_READY is not a dual-purpose pin.
• Updated configuration pin screenshot in the Specifying Optional Configuration Pins section.
• Revised SDM I/O Pins for Power Management and SmartVID topic. Updated screenshot and list of recommended devices.
• Added clarifying text in the OSC_CLK_1 Clock Input topic. If you use transceivers, you must provide an external clock to
the OSC_CLK_1 clock input.
•
Globally added AS_nRST configuration pin.
• Updated AS Configuration.
— Added text describing QSPI flash reset.
—
Removed 108 MHz support from the Supported configuration clock source and AS_CLK Frequencies in Intel Agilex
Devices table.
—
Updated AS_CLK supported frequency from 133 MHz to 166 MHz.
— Updated AS mode maximum data rate from 532 MHz to 664 MHz.
•
Globally added support for new AS_CLK frequency. The frequency value is 166 MHz. Globally updated tables specifying AS
configuration clock source range.
• Updated Programming Serial Flash Devices using the AS Interface and Debugging Guidelines for the AS Configuration
Scheme with the following text: When you power up the Intel Agilex with an empty serial flash device and use the AS
interface to program the .rpd file into this serial flash device, you must power cycle the Intel Agilex device to configure the
device from the flash successfully.
• Added new debugging suggestions in the following topics:
— Debugging Guidelines for the Avalon-ST Configuration Scheme
— Debugging Guidelines for the AS Configuration Scheme
— Debugging Guidelines for the JTAG Configuration Scheme
• Added new debugging suggestion in the Debugging Guidelines for the JTAG Configuration Scheme stating that no external
components should drive nSTATUS signal low during power up.
• Corrected CFI flash memory device number in Generating and Programing a .pof into SFI Flash. The device number is
MT28EW.
continued...
9. Document Revision History for the Intel Agilex Configuration User Guide
683673 | 2021.10.29
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