Intel Altera MAX 10 FPGA - Page 16

Controls Description
Ethernet B MAC Indicates the Ethernet B MAC address of the board.
JTAG Chain Shows all the devices currently in the JTAG chain.
Qsys Memory Map Shows the memory map of the Platform Designer (Standard) system on
your board.
3. Board Test System
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MAX
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10 FPGA Development Kit User Guide
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