Intel Altera MAX 10 FPGA - Digital-To-Analog Converter

Board
Reference
(U10)
Schematic Signal Name I/O Standard Max 10
FPGA Pin
Number
Description
U10.83
ENETB_RX_COL
2.5V CMOS N2 MII Collision
U10.55
CLK_25_ENET
2.5V CMOS — 25 MHz Reference clock
U10.70
ENETB_LED_DUPLEX
2.5V CMOS — Duplex or collision LED
U10.76
ENETB_LED_LINK10
2.5V CMOS — 10 Mb link LED
U10.74
ENETB_LED_LINK100
2.5V CMOS P9 100 Mb link LED
U10.73
ENETB_LED_LINK1000
2.5V CMOS — 1000 Mb link LED
U10.58, 69
ENETB_LED_RX
2.5V CMOS — RX data active LED
U10.61, 65,
68
ENETB_LED_TX
2.5V CMOS — TX data active LED
U10.29
ENETB_MDI_P0
2.5V CMOS — MDI
U10.31
ENETB_MDI_N0
2.5V CMOS — MDI
U10.33
ENETB_MDI_P1
2.5V CMOS — MDI
U10.34
ENETB_MDI_N1
2.5V CMOS — MDI
U10.39
ENETB_MDI_P2
2.5V CMOS — MDI
U10.41
ENETB_MDI_N2
2.5V CMOS — MDI
U10.42
ENETB_MDI_P3
2.5V CMOS — MDI
U10.43
ENETB_MDI_N3
2.5V CMOS — MDI
A.8.2. Digital-to-Analog Converter
The MAX 10 FPGA comes with one external 16 bit digital-to-analog converter (DAC)
device with an SMA output.
The MAX 10 FPGA has two 12-bit successive approximation register (SAR) ADCs with
sample rate of 1 MSps. One potentiometer is connected to ADC1_CH6 to function as a
user-controlled DC, and it is connected to 2.5 V. To ensure performance evaluation of
the ADCs, the MAX 10 FPGA Development Kit has separate analog supply and split
partition for analog ground. An external 16-bit single channel DAC is connected to
Bank 7 to enable closed loop evaluation. The DAC uses a 3-wire serial interface that
operates at clock rates up to 30 MHz. It is compatible with standard serial peripheral
interface (SPI), quad SPI, Microwire, and digital signal processor (DSP) interfaces.
Table 29. Digital-to-Analog Converter Signals
Board
Reference
(U33)
Signal Name I/O Standard MAX 10
FPGA Pin
Number
Description
U33.5
DAC_SYNC
3.3 V U1.B10 Level-triggered control input (active
LOW). Frame synchronization signal
for the input data.
U33.6
DAC_SCLK
3.3 V A7 Serial clock input
U33.7
DAC_DIN
3.3 V A8 Serial data input
A. Development Kit Components
683460 | 2024.11.20
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10 FPGA Development Kit User Guide
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