Intel Altera MAX 10 FPGA - Document Revision History for the MAX 10 FPGA Development Kit User Guide

4. Document Revision History for the MAX 10 FPGA
Development Kit User Guide
Document
Version
Changes
2024.11.20 • Updated the Overview chapter:
— Updated Feature Summary.
— Added new topics: Block Diagram and Box Content.
— Added new Table: Ordering Information.
— Added new Figures: MAX 10 FPGA Development Kit—Top View and MAX 10 FPGA Development
Kit—Bottom View.
— Removed General Description.
• Added new topics to the Getting Started chapter:
— Before You Begin
— Handling the Board
— Software and Driver Installation
— Step 1: Connect to the Board Update Portal
— Step 2: Update the User Software Portion
• Updated all figures in the Board Test System chapter.
• Updated the following figures in the appendix chapter Development Kit Components for clarity:
— Figure: Jumper J7 on the Top of the Board (Detail)
— Figure: Switches on the Bottom Board (Detail)
— Figure: Power Distribution System
• Updated and retitled appendix chapter Additional Information to Safety and Regulatory Compliance
Information:
— Added new topics—Safety and Regulatory Information, Safety Warnings, and Safety Cautions.
— Updated Compliance Information.
• Restructured the document to improve clarity and for ease of reference.
• Updated for the latest branding standards.
Date Version Changes
September 2017 2017.09.07 Updated I/O standard voltage values in the On-Board
Oscillators table in On-Board Oscillators.
January 2017 2017.01.04 Corrected the following pin assignments in
"10/100/1000 Ethernet PHY":
• ENETA_TX_D1 on pin P5
• ENETA_RX_ER on pin U2
• ENET_MDIO on pin Y5
• ENETB_TX_D2 on pin U3
• ENETB_RS_D3 on pin R7
November 2015 2015.11.06 • Updated "USB to UART" section.
• Added note to "General User Input/Output section".
continued...
683460 | 2024.11.20
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