Intel Altera MAX 10 FPGA - The HSMC Tab

3.5. The HSMC Tab
The HSMC tab allows you to test the CMOS port.
Figure 10. The HSMC Tab
Table 6. Controls on the HSMC Tab
Control Description
Status Pattern sync: Shows the pattern synced or not synced state. The pattern
is considered synced when the start of the data sequence is detected.
Port CMOS: The CMOS port is available for tests.
Data Type The following data types are available for analysis:
• prbs7: Selects pseudo-random 7-bit sequences.
• prbs15: Selects pseudo-random 15-bit sequences.
• prbs23: Selects pseudo-random 23-bit sequences.
continued...
3. Board Test System
683460 | 2024.11.20
Send Feedback
MAX
®
10 FPGA Development Kit User Guide
19