Intel Altera MAX 10 FPGA - Featured Device; Configuration

Board Reference Type Description
Analog
J18, J19 SMA inputs Two FPGA analog-to-digital converter (ADC).
J20 Header 2x10 ADC.
POT1 Potentiometer Input to ADC.
J1 SMA output External 16 bit digital-to-analog converter (DAC)
device.
Video and Display Ports
U8 HDMI video output 19-pin HDMI connector which provides a HDMI v1.4
video output of up to 1080p through an ADI (Analog
Devices, Inc) PHY.
Power Supply
J15 DC input jack Accepts 12 V DC power supply.
SW3 Power switch Switch to power on or off the board when power is
supplied from the DC input jack.
A.2. Featured Device
The MAX 10 FPGA development board features the MAX 10 10M50DAF484I6G device
(U1) in a 484-pin FineLine BGA package.
Table 15. MAX 10 FPGA 10M50DAF484I6G Features
ALMs Equivalent
LEs
M9K
Memory
(Kb)
Total RAM
(Kb)
18-bit x 18-
bit
Multipliers
PLLs Transceiver
s
Package Type
50,000 50 1,638 736 144 4 — FineLine BGA 484
pins
A.3. Configuration
The MAX 10 FPGA Development Kit supports two configuration methods:
•
Configuration by downloading a .sof file to the FPGA. Any power cycling of the
FPGA or reconfiguration powers up the FPGA to a blank state.
•
Programming of the on-die FPGA Configuration Flash Memory (CFM) via a .pof
file. Any power cycling of the FPGA or reconfiguration powers up the FPGA in self-
configuration mode, using the files stored in the CFM.
You can use two different Intel FPGA Download Cable hardware components to
program the .sof or .pof files:
• Embedded Intel FPGA Download Cable II, type-B connector (J12).
• JTAG header (J14). Use an external Intel FPGA Download Cable, Intel FPGA
Download Cable II, or Intel FPGA Ethernet Cable. The external download cable
connects to the board through the JTAG header (J14).
A. Development Kit Components
683460 | 2024.11.20
MAX
®
10 FPGA Development Kit User Guide
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