Intel Altera MAX 10 FPGA - Page 24

Table 9. ADC 2 Channel Connection
Dedicated Channel SMA Connector
ADC 2 ANAIN2_SMA(J19)
Channel 0 ADC1_CH0(J20.2)
Channel 1 ADC1_CH1(J20.4)
Channel 2 ADC1_CH2(J20.6)
Channel 3 ADC1_CH2(J20.8)
Channel 4 ADC1_CH4(J20.12)
Channel 5 ADC1_CH4(J20.14)
Channel 6 ADC1_CH6(J20.16)
Channel 7 ADC1_CH7(J20.18)
3. Board Test System
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10 FPGA Development Kit User Guide
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