Intel Altera MAX 10 FPGA - Page 56

Board Reference
(U5 & U6)
Schematic Signal Name I/O Standard MAX 10
FPGA Pin
Number
Description
U5.M3 - U6.J3
DDR3_BA2
1.5 V SSTL W22 Bank address bus
U5.K3 - U6.G3
DDR3_CASn
1.5 V SSTL U19 Row address bus
U5.K9 - U6.G9
DDR3_CKE
1.5 V SSTL W20 Clock enable
U5.J7 - U6.F7
DDR3_CLK_P
Differential 1.5 V
SSTL
D18 Differential output clock
U5.K7 - U6.G7
DDR3_CLK_N
Differential 1.5 V
SSTL
E18 Differential output clock
U5.L2 - U6.H2
DDR3_CSn
1.5 V SSTL Y22 Chip select
U5.E7
DDR3_DM0
1.5 V SSTL J15 Write mask byte lane 0
U5.D3
DDR3_DM1
1.5 V SSTL N19 Write mask byte lane 1
U6.B7
DDR3_DM2
1.5 V SSTL T18 Write mask byte lane 2
U5.E3
DDR3_DQ0
1.5 V SSTL J18 Data bus byte lane 0
U5.F7
DDR3_DQ1
1.5 V SSTL K20 Data bus byte lane 0
U5.F2
DDR3_DQ2
1.5 V SSTL H18 Data bus byte lane 0
U5.F8
DDR3_DQ3
1.5 V SSTL K18 Data bus byte lane 0
U5.H3
DDR3_DQ4
1.5 V SSTL H19 Data bus byte lane 0
U5.H8
DDR3_DQ5
1.5 V SSTL J20 Data bus byte lane 0
U5.G2
DDR3_DQ6
1.5 V SSTL H20 Data bus byte lane 0
U5.H7
DDR3_DQ7
1.5 V SSTL K19 Data bus byte lane 0
U5.D7
DDR3_DQ8
1.5 V SSTL L20 Data bus byte lane 1
U5.C3
DDR3_DQ9
1.5 V SSTL M18 Data bus byte lane 1
U5.C8
DDR3_DQ10
1.5 V SSTL M20 Data bus byte lane 1
U5.C2
DDR3_DQ11
1.5 V SSTL M14 Data bus byte lane 1
U5.A7
DDR3_DQ12
1.5 V SSTL L18 Data bus byte lane 1
U5.A2
DDR3_DQ13
1.5 V SSTL M15 Data bus byte lane 1
U5.B8
DDR3_DQ14
1.5 V SSTL L19 Data bus byte lane 1
U5.A3
DDR3_DQ15
1.5 V SSTL N20 Data bus byte lane 1
U6.B3
DDR3_DQ16
1.5 V SSTL R14 Data bus byte lane 2
U6.C7
DDR3_DQ17
1.5 V SSTL P19 Data bus byte lane 2
U6.C2
DDR3_DQ18
1.5 V SSTL P14 Data bus byte lane 2
U6.C8
DDR3_DQ19
1.5 V SSTL R20 Data bus byte lane 2
U6.E3
DDR3_DQ20
1.5 V SSTL R15 Data bus byte lane 2
U6.E8
DDR3_DQ21
1.5 V SSTL T19 Data bus byte lane 2
U6.D2
DDR3_DQ22
1.5 V SSTL P15 Data bus byte lane 2
continued...
A. Development Kit Components
683460 | 2024.11.20
MAX
®
10 FPGA Development Kit User Guide
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