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Inventec N800G3 - Memory Reference Code Checkpoints

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04/01/2015 Inventec Corp. Confidential 76
0x54
Unspecified memory initialization error.
0x55
Memory not installed
0x56
Invalid CPU type or Speed
0x57
CPU mismatch
0x58
CPU self test failed or possible CPU cache error
0x59
CPU micro-code is not found or micro-code update is failed
0x5A
Internal CPU error
0x5B
reset PPI is not available
0x5C ~ 0x5F
Reserved for future AMI error codes
4.2.5. Memory Reference Code Checkpoints
Checkpoint
Description
0xB0
STS_DIMM_DETECT: Detect DIMM population
0xB1
STS_CLOCK_INIT: Set DDR frequency
0xB2
STS_SPD_DATA: Gather remaining SPD data
0xB3
STS_GLOBAL_EARLY: Program registers on the memory
controller level
0xB4
STS_RANK_DETECT: Evaluate RAS modes and save rank
information
0xB5
STS_CHANNEL_EARLY: Program registers on the channel
level
0xB6
STS_DDRIO_INIT: DDRIO Initialization sequence
0xB7
STS_DDR_CHANNEL_TRAINING: Train DDR
0xB8
STS_INIT_THROTTLING: Initialize CLTT/OLTT
0xB9
STS_MEMBIST: Hardware memory test and init
0xBA
STS_MEMINIT: Execute memory init
0xBB
STS_DDR_MEMMAP: Program memory map and
interleaving
0xBC
STS_RAS_CONFIG: Program RAS configuration
0xBD
STS_GET_MARGINS:
0xBF
STS_MRC_DONE: MRC is done

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