in the VCF. All spine devices have at least one direct VCP connection to each leaf device
in the VCF. See “Connecting a QFX5110 Device in a QFX5110 Virtual Chassis Fabric” on
page 96 for a cabling diagram.
Related
Documentation
QFX5110 Field-Replaceable Units on page 15•
• Channelizing Interfaces
• QFX5110 Access Port and Uplink Port LEDs on page 16
• Connecting QFX5110 and QFX5100 Members in a QFX5110 Virtual Chassis on page 95
• Connecting a QFX5110 Device in a QFX5110 Virtual Chassis Fabric on page 96
QFX5110-32Q Port Panel
The port panel of the QFX5110-32Q primarily comprises 28 quad small form-factor
pluggableplus (QSFP+)ports and 4 quad small form-factorpluggable solution (QSFP28)
ports. The mixture of QSFP+ and QSFP28 ports allows for flexible configuration as either
32 ports of 40-Gigabit Ethernet or 20 ports of 40-Gigabit Ethernet and 4 ports of
100-Gigabit Ethernet for high-speed uplinks. The port panel also provides a central
location for the Precision Time Protocol (PTP) connections to a grandmaster clock.
This topic describes:
•
Switch Overview on page 12
•
Switch Ports on page 13
•
Channelizing Interfaces on page 13
•
Virtual Chassis and Virtual Chassis Fabric on page 15
Switch Overview
The ports on the QFX5110-32Q support 40-Gbps or 100-Gbps speeds natively. Of the 28
QSFP+ ports, 0 through 19also support 10-Gbps speeds when the ports are configured
as Flexi-pic and channelized using QSFP+ to SFP+ DAC breakout (DACBO) cables.
Although all network ports can be configured as either uplink or as access ports, best
practice is to configure the four QSFP28 ports (28 through 31) as uplinks to take advantage
of the 100-Gbps speeds.
The port panel also provides PTP connections to a grandmaster clock. There are also
10-MHz pulses-per-second (PPS) SubMiniature B (SMB) input and output connections
to measure the timing drift to and from the grandmaster clock.
Figure 4 on page 13 shows the port panel of the QFX5110-32Q.
Copyright © 2017, Juniper Networks, Inc.12
QFX5110 Switch Hardware Guide
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