Lattice Semiconductor ECP5 - Page 6

ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
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6 FPGA-TN-02035-1.3
Figures
Figure 2.1. External Interface Definitions ........................................................................................................................... 10
Figure 3.1. ECP5 and ECP5-5G Device Clocking Diagram .................................................................................................... 11
Figure 3.2. DDRDLL Connectivity ........................................................................................................................................ 12
Figure 5.1. GDDRX1_RX.SCLK.Centered Interface (Static Delay) ........................................................................................ 15
Figure 5.2. GDDRX1_RX.SCLK.Centered Interface (Dynamic Data Delay) ........................................................................... 15
Figure 5.3. GDDRX1_RX.SCLK.Aligned Interface (Static Delay) ........................................................................................... 16
Figure 5.4. GDDRX1_RX.SCLK.Aligned Interface (Dynamic Data/Clock Delay) ................................................................... 17
Figure 5.5. GDDRX2_RX.ECLK.Centered Interface (Static Delay) ........................................................................................ 18
Figure 5.6. GDDRX2_RX.ECLK.Centered Interface (Dynamic Data Delay) ........................................................................... 18
Figure 5.7. GDDRX2_RX.ECLK.Aligned Interface (Static Delay) ........................................................................................... 19
Figure 5.8. GDDRX2_RX.ECLK.Aligned Interface (Dynamic Data/Clock Delay) ................................................................... 19
Figure 5.9. GDDRX2_RX.MIPI .............................................................................................................................................. 20
Figure 5.10. GDDRX71_RX.ECLK Interface .......................................................................................................................... 21
Figure 5.11. GDDRX1_TX.SCLK.Aligned Interface ............................................................................................................... 22
Figure 5.12. GDDRX1_TX.SCLK.Centered Interface ............................................................................................................. 23
Figure 5.13. GDDRX2_TX.ECLK.Aligned Interface ............................................................................................................... 23
Figure 5.14. GDDRX2_TX.ECLK.Centered Interface ............................................................................................................ 24
Figure 5.15. GDDRX71_TX.ECLK Interface .......................................................................................................................... 25
Figure 5.16. RX Centered Interface Timing ......................................................................................................................... 27
Figure 5.17. RX Aligned Interface Timing ............................................................................................................................ 28
Figure 5.18. tCO Min and Max Timing Analysis .................................................................................................................. 29
Figure 5.19. Transmit Centered Interface Timing ............................................................................................................... 29
Figure 5.20. Transmit Aligned Interface Timing .................................................................................................................. 30
Figure 6.1. Typical DDR2/DDR3/DDR3L Memory Interface ................................................................................................ 31
Figure 6.2. Typical LPDDR2/LPDDR3 Memory Interface ..................................................................................................... 32
Figure 6.3. DQ-DQS During Read ........................................................................................................................................ 32
Figure 6.4. DQ-DQS During Write ....................................................................................................................................... 32
Figure 6.5. DQ-DQS Grouping ............................................................................................................................................. 34
Figure 6.6. DQSBUF Block Functions ................................................................................................................................... 35
Figure 6.7. READ Signal Training Process ............................................................................................................................ 37
Figure 6.8. DDR2, DDR3/DDR3L, LPDDR2, and LPDDR3 Read Side Implementation .......................................................... 39
Figure 6.9. DDR2, DDR3/DDR3L, LPDDR2, and LPDDR3 Write Side (DQ, DQS, and DM) .................................................... 40
Figure 6.10. DDR2, DDR3/DDR3L Address, Command, and Clock Generation ................................................................... 41
Figure 6.11. LPDDR2 Output for CA Generation ................................................................................................................. 42
Figure 6.12. LPDDR2 Output for CSN, CKE, and CLOCK Generation ................................................................................... 43
Figure 6.13. LPDDR3 Output Side for CA Generation ......................................................................................................... 43
Figure 6.14. LPDDR3 Output Side for CSN, CKE, ODT, and CLOCK Generation ................................................................... 44
Figure 7.1. Clarity Design Main Window ............................................................................................................................. 49
Figure 7.2. SDR Option Selected in the Catalog Tab of Clarity Designer ............................................................................. 50
Figure 7.3. SDR Configuration Tab ...................................................................................................................................... 51
Figure 7.4. DDR_Generic Option Selected in the Catalog Tab of Clarity Designer .............................................................. 53
Figure 7.5. DDR_Generic Pre-Configuration Tab ................................................................................................................ 53
Figure 7.6. DDR_Generic Configuration Tab ....................................................................................................................... 54
Figure 7.7. GDDR_7:1 Option Selected in the Catalog Tab of Clarity Designer .................................................................. 57
Figure 7.8. GDDR_7:1 LVDS Configuration Tab ................................................................................................................... 57
Figure 7.9. DDR_MEM Option Selected in the Catalog Tab of Clarity Designer ................................................................. 58
Figure 7.10. DDR_MEM Configuration Tab ......................................................................................................................... 59
Figure 7.11. DDR_MEM Clock/Address/Command Tab ...................................................................................................... 61
Figure 7.12. DDR_MEM Advanced Settings Tab ................................................................................................................. 62
Figure 7.13. DDR Modules Paced Using Clarity Design Planner.......................................................................................... 63
Figure 8.1. DELAYF Primitive ............................................................................................................................................... 65
Figure 8.2. DELAYG Primitive .............................................................................................................................................. 65