Lattice Semiconductor ECP5 - On-Board Clock Capabilities; SERDES Block

ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
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FPGA-TN-02035-1.3 7
Figure 8.3. DDRDLLA Primitive ............................................................................................................................................ 66
Figure 8.4. DLLDELD Primitive ............................................................................................................................................ 67
Figure 8.5. IDDDRX1F Primitive .......................................................................................................................................... 68
Figure 8.6. IDDRX2F Primitive ............................................................................................................................................. 69
Figure 8.7. IDDR71B ............................................................................................................................................................ 69
Figure 8.8. ODDRX1F........................................................................................................................................................... 70
Figure 8.9. ODDRX2F........................................................................................................................................................... 70
Figure 8.10. ODDR71B Primitive ......................................................................................................................................... 71
Figure 8.11. DQSBUFM Primitive ........................................................................................................................................ 72
Figure 8.12. IDDRX2DQA Primitive ..................................................................................................................................... 74
Figure 8.13. ODDRX2DQA ................................................................................................................................................... 75
Figure 8.14. ODDRX2DQSB Primitive .................................................................................................................................. 75
Figure 8.15. TSHX2DQA Primitive ....................................................................................................................................... 76
Figure 8.16. TSHX2DQSA Primitive ..................................................................................................................................... 76
Figure 8.17. OSHX2A Primitive ........................................................................................................................................... 77
Figure 9.1. GDDR_SYNC Ports ............................................................................................................................................. 78
Figure 9.2. RX_SYNC Ports .................................................................................................................................................. 79
Figure 9.3. MEM_SYNC Ports .............................................................................................................................................. 80
Figure 9.4. BW_ALIGN Ports ............................................................................................................................................... 80
Figure 9.5. MIPI_FILTER Ports ............................................................................................................................................. 81