Lattice Semiconductor ECP5 - FPGA Test Pins and Switches; General Purpose DIP Switches

ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
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8 FPGA-TN-02035-1.3
Tables
Table 4.1. Generic High-Speed I/O DDR Interfaces ............................................................................................................. 14
Table 6.1. DDR Memory Configurations Support ............................................................................................................... 33
Table 6.2. DDRDLL Connectivity .......................................................................................................................................... 35
Table 6.3. DDRDLL Connectivity .......................................................................................................................................... 36
Table 6.4. I/O Standards for DDR Memory ......................................................................................................................... 45
Table 7.1. SDR Configuration Parameters ........................................................................................................................... 52
Table 7.2. DDR_Generic Pre-Configuration Parameters ..................................................................................................... 54
Table 7.3. DDR_Generic Configuration Tab Parameters ..................................................................................................... 55
Table 7.4. Clarity Designer DDR_Generic Interface Selection ............................................................................................ 56
Table 7.5. GDDR_7:1 LVDS Configuration Parameters ....................................................................................................... 58
Table 7.6. DDR_MEM Configuration Tab Parameters ........................................................................................................ 60
Table 7.7. DDR_MEM Clock/Address/Command Parameters ............................................................................................ 61
Table 7.8. DDR_MEM Advanced Settings Tab Parameters ................................................................................................. 62
Table 8.1. Software Primitives ............................................................................................................................................ 64
Table 8.2. DELAYF Port List ................................................................................................................................................. 65
Table 8.3. DELAYG Port List ................................................................................................................................................. 65
Table 8.4. DELAYF and DELAYG Attributes .......................................................................................................................... 66
Table 8.5. DDRDLLA Port List .............................................................................................................................................. 67
Table 8.6. DDRDLL Attributes ............................................................................................................................................. 67
Table 8.7. DLLDELD Port List ............................................................................................................................................... 67
Table 8.8. DLLDELD Attributes ............................................................................................................................................ 68
Table 8.9. IDDRX1F Port List ............................................................................................................................................... 68
Table 8.10. IDDRX2F Port List ............................................................................................................................................. 69
Table 8.11. IDDRX2F Port List ............................................................................................................................................. 69
Table 8.12. ODDRX1F Port List ............................................................................................................................................ 70
Table 8.13. ODDRX2F Port List ............................................................................................................................................ 70
Table 8.14. ODDR71B Port List ........................................................................................................................................... 71
Table 8.15. DQSBUF Port List .............................................................................................................................................. 72
Table 8.16. DQSBUFM Attributes ....................................................................................................................................... 73
Table 8.17. Summary of all DDR Memory Primitives .......................................................................................................... 73
Table 8.18. DQSBUF Port List .............................................................................................................................................. 74
Table 8.19. Memory Primitive Attributes ........................................................................................................................... 74
Table 8.20. ODDRX2DQA Port List ...................................................................................................................................... 75
Table 8.21. ODDRX2DQA Port List ...................................................................................................................................... 76
Table 8.22. TSHX2DQA Port List .......................................................................................................................................... 76
Table 8.23. TSHX2DQSA Port List ........................................................................................................................................ 77
Table 8.24. OSHX2A Port List .............................................................................................................................................. 77
Table 9.1. List of Soft IPs supported ................................................................................................................................... 78
Table 9.2. Soft IP Used in Each Interface ............................................................................................................................ 78
Table 9.3. GDDR_SYNC Port List description ...................................................................................................................... 79
Table 9.4. GDDR_SYNC Port List description ...................................................................................................................... 79
Table 9.5. MEM_SYNC Port Description ............................................................................................................................. 80
Table 9.6. BW_ALIGN Port Description ............................................................................................................................... 81
Table 9.7. MIPI_FILTER Port Description ............................................................................................................................ 82