Neoway N75 - Spi; Figure 3-33 SPI Connection

N75
Hardware User Guide
Copyright © Neoway Technology Co., Ltd
39
rising
t(suauxdin)
PCM_DIN set-up time to PCM_CLK falling
70
/
/
ns
t(hauxdin)
Hold time from PCM_CLK low to
PCM_DIN high
20
/
/
ns
t(pauxdout)
Delay time from PCM_CLK PCM_DOUT
valid
/
/
50
ns
3.3.7 SPI
Signal
Pin
I/O
Function
Remarks
SPI_CLK_BLSP2
84
DO
Clock signal
Max. 50 MHz
SPI_MISO_BLSP2
85
DI
Master input
Leave this pin floating if it is not used.
SPI_MOSI_BLSP2
86
DO
Master output
Leave this pin floating if it is not used.
SPI_CS_N_BLSP2
87
DO
Chip select
Leave this pin floating if it is not used.
The SPI interface operates at 1.8 V. It supports a maximum frequency of 50 MHz and only host mode.
Figure 3-33 and table show the SPI connection.
Figure 3-33 SPI connection
SPI_MOSI
SPI_CS_N
SPI_CLK
N75 module
(host)
SPI_MISO
MOSI
MISO
CLK
CS
SPI device
(device)
Schematic Guidelines
⚫
Note the SPI signal direction.
⚫
If the levels of slave SPI device and N75 do not match, add a level shifting circuit. Refer to
Figure 3-20 if the SPI speed does not exceed 20 MHz. Select other high-speed level shifting
chipsets if the speed exceeds 20 MHz.