Neoway N75 - I2 C; Figure 3-34 SPI Timing; Table 3-9 Timing Parameters of SPI Interface

N75
Hardware User Guide
Copyright © Neoway Technology Co., Ltd
40
PCB Design Guidelines
⚫
Do not cross other traces if possible. If crossing is inevitable, route the SPI traces perpendicular
to other traces.
⚫
Keep SPI traces far away from areas that might introduce ESD.
⚫
Surround signal traces with ground.
Figure 3-34 and Table 3-9 shows SPI timing and parameters respectively.
Figure 3-34 SPI timing
Table 3-9 Timing parameters of SPI interface
Timing Parameter
Minimum
Value
Typical
Value
Maximum
Value
Unit
T
Clock cycle (max. 50MHz)
20.0
/
/
ns
t(ch)
Clock high time
9.0
/
/
ns
t(cl)
Clock low time
9.0
/
/
ns
t(mov)
Output valid time
-5.0
/
5.0
ns
t(mis)
Input set-up time
5.0
/
/
ns
t(mih)
Input hold time
1.0
/
/
ns
3.3.8 I2C
Signal
Pin
I/O
Function
Remarks
I2C_4_SDA
81
B
I2C data
Embed a 2.2 kΩ pulled up resistor internally.
I2C_4_SCL
82
DO
I2C clock
Embed a 2.2 kΩ pulled up resistor internally.
I2C operates at 1.8V and complies with I2C Specification, version5.0, October 2012. Theoretical rate
is up to 1 Mbps.
The I2C interface is open-drain driven and connected through an internal pull-up resistor. If you use
other pins to multiplex I2C interface, reserve a place for the external pull-up resistor. It can be used in
T
t(mov)
t(mis) t(mih)
SPI_CS_N
SPI_CLK
SPI_MOSI
SPI_MISO