Neoway N75 - Figure 3-39 Connection between MDIO and PHY; Figure 3-40 MDIO Input Timing; Figure 3-41 MDIO Output Timing

N75
Hardware User Guide
Copyright © Neoway Technology Co., Ltd
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MDIO and PHY chipset signals share the same pins with USIM2. The hardware does not support both
functions simultaneously. Figure 3-39 shows the connection between MDIO and PHY chipset.
Figure 3-39 Connection between MDIO and PHY
MDIO_DATA
MDIO_CLK
ETH_RST_N
ETH_INT_N
N75 module
MDIO_DATA
MDIO_CLK
RST_N
INT_N
PHY chipset
SGMII_VCC
1.5kΩ
10kΩ
VDD_1P8
R353
R354
U306
MDIO can control one MAC or up to 32 PHY devices. It supports a maximum frequency of 2.5 MHz
and 1.8V/2.85V auto-adaption. Figure 3-40 and Figure 3-41 show MDIO input/output timing.
Figure 3-40 MDIO input timing
Figure 3-41 MDIO output timing
ViL(MAX)
ViH(MIN)
10ns MIN 10ns MIN
ViL(MAX)
ViH(MIN)
MDIO_CLK
MDIO_DATA
ViL(MAX)
ViH(MIN)
0ns MIN
300ns MAX
ViL(MAX)
ViH(MIN)
MDIO_CLK
MDIO_DATA