Service Modes, Error Codes, and Fault Finding
EN 31BJ3.0E PA 5.
Figure 5-12 “Semi Stand-by” to “Stand-by” flowchart
G_15960_133.eps
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action holder: MIPS
autonomous action
action holder: St-by
transfer Wake up reasons to the
Stand by µP.
Images are re-transferred to DDR-RAM from
Flash RAM (verification through checksum)
Stand by
Semi Stand by
MIPS image completes the application reload,
stops DDR-RAM access, puts itself in a
sleepmode and signals the standby µP when the
standby mode can be entered.
Disable all supply related protections and switch off
the +2V5, +3V3 DC/DC converter.
DDR-RAM is put in self refresh mode and the images
are kept in the hibernating DDR-RAM.
Switch OFF all supplies by switching HIGH the POD-
MODE and the ON-MODE I/O lines.
Switch Viper in reset state
Important remark:
release reset audio and sound-
enable 10 sec after entering
standby to save power
switch off the remaining DC/DC converters
Wait 5ms
Wait 5ms
For PDP this means CPUGO
becomes low.
Wait 10ms
Switch the NVM reset line HIGH.
Delay transition until ramping down of ambient light is
finished. *)
Switch ambient light to passive mode with RGB
values on zero. *)
*) If this is not performed and the set is
switched to standby when the ramping of
the EPLD is still ongoing, the lights will
remain lit in standby.
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