User Manual
E727T0005, valid for E-727
BRO, 2019-06-28
Physik Instrumente (PI) GmbH & Co. KG, Auf der Roemerstrasse 1, 76228 Karlsruhe, Germany Page 160 / 240
Phone +49 721 4846-0, Fax +49 721 4846-1019, Email info@pi.ws, www.pi.ws
DCLK: Data Output Clock
The PI-controller returns the SCLK as DCLK line (see next figure). The host can use the DCLK line for
the reception of the MISO line. With this method the delays caused by the transmission line, the
LVDS-divers and receivers can be compensated. For this reason higher data rates are possible with
DCLK.
It is possible to run the interface without using the DCLK line. But in this case the delays on the
transmission lines and the driver and receiver components become the limiting factor for the
transmission rate. For proper data transfer it is therefore recommended to use the DCLK line in
every case with data rates higher than 15 MHz.
Serial Transmission
The following diagram shows the transfer of a complete command packet. LDAT is active low
throughout a command packet transmission. CS is set low before a new word is transferred and set
high when a word transfer is completed. SCLK is active only when data bits are transferred.
To Next Page
Loading...
Need help?
General
