RL78/G13 CHAPTER 3 CPU ARCHITECTURE
R01UH0146EJ0100 Rev.1.00 102
Sep 22, 2011
Figure 3-4. Memory Map (R5F100xE, R5F101xE(x = 6 to 8, A to C, E to G, J, L))
00000H
EFFFFH
F0000H
F07FFH
F0800H
F0FFFH
F1000H
FEEFFH
FEF00H
FFEDFH
FFEE0H
FFEFFH
FFF00H
FFFFFH
00000H
0007FH
00080H
000BFH
000C0H
000C3H
000C4H
00FFFH
01000H
0107FH
01080H
010BFH
010C0H
010C3H
010C4H
0FFFFH
0FFFFH
10000H
Special function register (SFR)
256 bytes
RAM
Notes 1, 2
4 KB
General-purpose register
32 bytes
Code flash memory
64 KB
Special function register (2nd SFR)
2 KB
Mirror
51.75 KB
Vector table area
128 bytes
CALLT table area
64 bytes
Program area
Option byte area
Note 3
4 bytes
Vector table area
128 bytes
CALLT table area
64 bytes
Option byte area
Note 3
4 bytes
Program area
Reserved
Reserved
Program
memory
space
Data memory
space
On-chip debug security
ID setting area
Note 3
10 bytes
01FFFH
Boot cluster 0
Note 4
Boot cluster 1
010CDH
010CEH
On-chip debug security
ID setting area
Note 3
10 bytes
000CDH
000CEH
Data flash memory
Note 5
4 KB
F1FFFH
F2000H
Notes 1. Use of the area FEF00H to FF309H is prohibited when using the self-programming function and data flash
function, because this area is used for self-programming library.
2. Instructions can be executed from the RAM area excluding the general-purpose register area.
3. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security
IDs to 000C4H to 000CDH.
When boot swap is used: Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the
on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH.
4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 25.6 Security Setting).
5. R5F100xE only.
Caution When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS
= 1), be sure to initialize the used RAM area + 10 bytes.
<R>
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