RL78/G13 CHAPTER 21 VOLTAGE DETECTOR
R01UH0146EJ0100 Rev.1.00 897
Sep 22, 2011
21.4.3 When used as interrupt and reset mode
• When starting operation
Specify the operation mode (the interrupt and reset (LVIMDS1, LVIMDS0 = 1, 0)) and the detection voltage
(V
LVIH, VLVIL) by using the option byte 000C1H/010C1H.
Start in the following initial setting state.
• Set bit 7 (LVISEN) of the voltage detection register (LVIM) to 0 (disable rewriting of voltage detection level
register (LVIS))
• When the option byte LVIMDS1 is set to 1 and LVIMDS0 is clear to 0, the initial value of the LVIS register is
set to 00H.
Bit 7 (LVIMD) is 0 (interrupt mode).
Bit 0 (LVILV) is 0 (high-voltage detection level: V
LVIH).
Caution The LVIRF flag may become 1 from the beginning due to the power-on waveform.
For details of the RESF register, see CHAPTER 19 RESET FUNCTION.
Figure 21-6 shows the timing of the internal reset signal and interrupt signal generated by the voltage detector.
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