RL78/G13 CHAPTER 6 TIMER ARRAY UNIT
R01UH0146EJ0100 Rev.1.00 334
Sep 22, 2011
6.3 Registers Controlling Timer Array Unit
Timer array unit is controlled by the following registers.
• Peripheral enable register 0 (PER0)
• Timer clock select register m (TPSm)
• Timer mode register mn (TMRmn)
• Timer status register mn (TSRmn)
• Timer channel enable status register m (TEm)
• Timer channel start register m (TSm)
• Timer channel stop register m (TTm)
• Timer input select register 0 (TIS0)
• Timer output enable register m (TOEm)
• Timer output register m (TOm)
• Timer output level register m (TOLm)
• Timer output mode register m (TOMm)
• Input switch control register (ISC)
• Noise filter enable registers 1, 2 (NFEN1, NFEN2)
• Port mode register (PMxx)
Note
• Port register (Pxx)
Note
Note The port mode registers (PMxx) and port registers (Pxx) to be set differ depending on the product. For details,
see 6. 3 (15) Port mode registers 0, 1, 3, 4, 6, 10, 14 (PM0, PM1, PM3, PM4, PM6, PM10, PM14).
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
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