RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0146EJ0100 Rev.1.00 695
Sep 22, 2011
12.8.4 Stop condition generation
After all data are transmitted to or received from the target slave, a stop condition is generated and the bus is released.
(1) Processing flow
Figure 12-115. Timing Chart of Stop Condition Generation
Stop condition
STmn
SEmn
SOEmn
SCLr output
SDAr output
Operation
stop
SOmn
bit manipulation
CKOmn
bit manipulation
SOmn
bit manipulation
Note
Note During a receive operation, the SOEmn bit of serial output enable register m (SOEm) is cleared to 0 before
receiving the last data.
Figure 12-116. Flowchart of Stop Condition Generation
Starting generation of stop condition.
End of IIC communication
Writing 1 to the STmn bit to clear
(the SEmn bit is cleared to 0)
Writing 0 to the SOEmn bit
Writing 1 to the SOmn bit
Writing 1 to the CKOmn bit
Writing 0 to the SOmn bit
Completion of data
transmission/data reception
Wait
Secure a wait time so that the specifications of
I
2
C on the slave side are satisfied.
Operation is stopped
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