Renesas RL78/G13

RL78/G13 CHAPTER 25 FLASH MEMORY
R01UH0146EJ0100 Rev.1.00 939
Sep 22, 2011
25.4.3 Procedure for accessing data flash memory
The data flash memory is initially stopped after a reset ends and cannot be accessed (read or programmed). To
access the memory, perform the following procedure:
<1> Write 1 to bit 0 (DFLEN) of the data flash control register (DFLCTL).
<2> Wait for the setup to finish.
The time setup takes differs for each main clock mode.
<Setup time for each main clock mode>
• HS (High-speed main): 5
μ s
• LS (Low-speed main): 720 ns
• LV (Low-voltage main): 10
μ s
<3> After the wait, the data flash memory can be accessed.
Cautions 1. Accessing the data flash memory is not possible during the setup time.
2. Before executing a STOP instruction during the setup time, temporarily clear DFLEN to 0.
<R>