Renesas RL78/G13 - Hardware Trigger Wait Mode (Select Mode, One-Shot Conversion Mode)

RL78/G13 CHAPTER 11 A/D CONVERTER
R01UH0146EJ0100 Rev.1.00 516
Sep 22, 2011
11.6.10 Hardware trigger wait mode (select mode, one-shot conversion mode)
<1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the
hardware trigger standby status.
<2> If a hardware trigger is input while in the hardware trigger standby status, A/D conversion is performed on the
analog input specified by the analog input channel specification register (ADS). The ADCS bit of the ADM0
register is automatically set to 1 according to the hardware trigger input.
<3> When A/D conversion ends, the conversion result is stored in the A/D conversion result register (ADCR, ADCRH),
and the A/D conversion end interrupt request signal (INTAD) is generated.
<4> After A/D conversion ends, the ADCS bit is automatically cleared to 0, and the A/D converter enters the stop
status.
<5> If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and
conversion restarts. The partially converted data is discarded.
<6> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D
conversion is interrupted, and A/D conversion is performed on the analog input respecified by the ADS register.
The partially converted data is discarded.
<7> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and
conversion restarts. The partially converted data is initialized.
<8> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, the system
enters the hardware trigger standby status, and the A/D converter enters the stop status. When ADCE = 0,
inputting a hardware trigger is ignored and A/D conversion does not start.
Figure 11-29. Example of Hardware Trigger Wait Mode (Select Mode, One-Shot Conversion Mode) Operation
Timing
ADCE
ADCS
ADS
INTAD
ADCR,
ADCRH
A/D
conversion
status
Hardware
trigger
ADCE is set to 1.
<1>
Stop status Stop status
Stop
status
Stop
status
Stop
status
Stop
status
Data 1
(ANI0)
Data 1
(ANI0)
Data 1
(ANI0)
Data 1
(ANI0)
Data 2
(ANI1)
Data 2
(ANI1)
Data 1
(ANI0)
Data 2
(ANI1)
Data 2
(ANI1)
Data 2
(ANI1)
Data 2
(ANI1)
Data 1
(ANI0)
Data 1
(ANI0)
The trigger is not
acknowledged.
Trigger
standby
status
A hardware trigger
is generated.
<2>
<2>
<2>
<2>
<2>
Conversion is
interrupted
and restarts.
<3>
A/D conversion
ends.
A hardware trigger is
generated during A/D
conversion operation.
<5>
<6>
<3>
<8>
<3>
Data 2
(ANI1)
ADS is rewritten
during A/D conversion
operation (from ANI0
to ANI1).
Conversion is
interrupted.
ADCS is cleared
to 0 during A/D
conversion
operation.
Trigger
standby
status
ADCS is automatically
cleared to 0 after
conversion ends.
<4>
<4> <4> <4>
ADCS is overwritten
with 1 during A/D
conversion operation.
<7>
<3>
Conversion is
interrupted
and restarts.
Conversion is
interrupted
and restarts.
<R>
<R>
<R>