Renesas RL78/G13 - Configuration of Timer Array Unit

RL78/G13 CHAPTER 6 TIMER ARRAY UNIT
R01UH0146EJ0100 Rev.1.00 328
Sep 22, 2011
6.2 Configuration of Timer Array Unit
Timer array unit includes the following hardware.
Table 6-1. Configuration of Timer Array Unit
Item Configuration
Timer/counter Timer count register mn (TCRmn)
Register Timer data register mn (TDRmn)
Timer input
TI00 to TI07, TI10 to TI17
Note 1
, RxD2 pin (for LIN-bus)
Timer output
TO00 to TO07, TO10 to TO17 pins
Note 1
, output controller
<Registers of unit setting block>
• Peripheral enable register 0 (PER0)
• Timer clock select register m (TPSm)
• Timer channel enable status register m (TEm)
• Timer channel start register m (TSm)
• Timer channel stop register m (TTm)
• Timer input select register 0 (TIS0)
• Timer output enable register m (TOEm)
• Timer output register m (TOm)
• Timer output level register m (TOLm)
• Timer output mode register m (TOMm)
Control registers
<Registers of each channel>
• Timer mode register mn (TMRmn)
• Timer status register mn (TSRmn)
• Input switch control register (ISC)
• Noise filter enable registers 1, 2 (NFEN1, NFEN2)
• Port mode register (PMxx)
Note 2
• Port register (Pxx)
Note 2
Notes 1. The presence or absence of timer I/O pins of channel 0 to 7 depends on the product. See Table 6-2 Timer
I/O Pins provided in Each Product for details.
2. The port mode registers (PMxx) and port registers (Pxx) to be set differ depending on the product. for
details, see 6. 3 (15) Port mode registers 0, 1, 3, 4, 6, 10, 14 (PM0, PM1, PM3, PM4, PM6, PM10, PM14).
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)