Renesas RL78/G13

RL78/G13 CHAPTER 3 CPU ARCHITECTURE
R01UH0146EJ0100 Rev.1.00 158
Sep 22, 2011
3.4.6 Register indirect addressing
[Function]
Register indirect addressing directly specifies the target addresses using the contents of the register pair specified
with the instruction word as an operand address.
[Operand format]
Identifier Description
−
[DE], [HL] (only the space from F0000H to FFFFFH is specifiable)
−
ES:[DE], ES:[HL] (higher 4-bit addresses are specified by the ES register)
Figure 3-39. Example of [DE], [HL]
Target memory
OP code
Memory
rp
FFFFFH
F0000H
Figure 3-40. Example of ES:[DE], ES:[HL]
OP code
Memory
FFFFFH
00000H
Target memory
ES
rp