Renesas RL78/G13

RL78/G13 CHAPTER 21 VOLTAGE DETECTOR
R01UH0146EJ0100 Rev.1.00 893
Sep 22, 2011
21.4 Operation of Voltage Detector
21.4.1 When used as reset mode
• When starting operation
Start in the following initial setting state.
Specify the operation mode (the reset mode (LVIMDS1, LVIMDS0 = 1, 1)) and the detection voltage (V
LVI) by
using the option byte 000C1H/010C1H.
• Set bit 7 (LVISEN) of the voltage detection register (LVIM) to 0 (disable rewriting of voltage detection level
register (LVIS))
• When the option byte LVIMDS1 and LVIMDS0 are set to 1, the initial value of the LVIS register is set to 81H.
Bit 7 (LVIMD) is 1 (reset mode).
Bit 0 (LVILV) is 1 (low-voltage detection level: V
LVI).
Figure 21-4 shows the timing of the internal reset signal generated by the voltage detector.
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