Renesas RL78/G13 - Chapter 3 Cpu Architecture; Memory Space

To Next Page

To Previous Page

RL78/G13 CHAPTER 3 CPU ARCHITECTURE

R01UH0146EJ0100 Rev.1.00 98

Sep 22, 2011

CHAPTER 3 CPU ARCHITECTURE

3.1 Memory Space

Products in the RL78/G13 can access a 1 MB memory space. Figures 3-1 to 3-10 show the memory maps.

Main Page

Default Chapter7
- Table of Contents7
Chapter 1 Outline20
- Features20
- Ordering Information22
- Pin Configuration (Top View)25
- 20-Pin Products25
- 24-Pin Products26
- 25-Pin Products27
- 30-Pin Products28
- 32-Pin Products29
- 36-Pin Products30
- 40-Pin Products31
- 44-Pin Products32
- 48-Pin Products33
- 52-Pin Products35
- 64-Pin Products36
- 80-Pin Products38
- 100-Pin Products39
- 128-Pin Products41
- Pin Identification42
- Block Diagram43
- 20-Pin Products43
- 24-Pin Products44
- 25-Pin Products45
- 30-Pin Products46
- 32-Pin Products47
- 36-Pin Products48
- 40-Pin Products49
- 44-Pin Products50
- 48-Pin Products51
- 52-Pin Products52
- 64-Pin Products53
- 80-Pin Products54
- 100-Pin Products55
- 128-Pin Products56
- Outline of Functions57
Chapter 2 Pin Functions63
- Pin Function List63
- 20-Pin Products64
- 24-Pin Products65
- 25-Pin Products66
- 30-Pin Products67
- 32-Pin Products69
- 36-Pin Products71
- 40-Pin Products73
- 44-Pin Products75
- 48-Pin Products77
- 52-Pin Products79
- 64-Pin Products81
- 80-Pin Products83
- 100-Pin Products86
- 128-Pin Products89
- Pins for each Product (Pins Other than Port Pins)93
- Description of Pin Functions99
- P00 to P07 (Port 0)99
- P10 to P17 (Port 1)100
- P20 to P27 (Port 2)101
- P30 to P37 (Port 3)101
- P40 to P47 (Port 4)102
- P50 to P57 (Port 5)104
- P60 to P67 (Port 6)104
- P70 to P77 (Port 7)105
- P80 to P87 (Port 8)106
- P90 to P97 (Port 9)106
- P100 to P106 (Port 10)106
- P110 to P117 (Port 11)107
- P120 to P127 (Port 12)107
- P130, P137 (Port 13)108
- P140 to P147 (Port 14)108
- P150 to P156 (Port 15)110
- VDD , Ev Dd0 , Ev Dd1 , V Ss , Ev Ss0 , Ev Ss1110
- Reset110
- Regc110
- Pin I/O Circuits and Recommended Connection of Unused Pins111
Chapter 3 Cpu Architecture117
- Memory Space117
- Internal Program Memory Space133
- Mirror Area136
- Internal Data Memory Space138
- Special Function Register (SFR) Area139
- Extended Special Function Register (2Nd SFR: 2Nd Special Function Register) Area139
- Data Memory Addressing140
- Processor Registers150
- Control Registers150
- General-Purpose Registers152
- ES and CS Registers154
- Special Function Registers (Sfrs)155
- Extended Special Function Registers (2Nd Sfrs: 2Nd Special Function Registers)161
- Instruction Address Addressing170
- Relative Addressing170
- Immediate Addressing170
- Table Indirect Addressing171
- Register Direct Addressing172
- Addressing for Processing Data Addresses173
- Implied Addressing173
- Register Addressing173
- Direct Addressing174
- Short Direct Addressing175
- SFR Addressing176
- Register Indirect Addressing177
- Based Addressing178
- Based Indexed Addressing181
- Stack Addressing182
Chapter 4 Port Functions183
- Port Functions183
- Port Configuration184
- Port 0186
- Port 1194
- Port 2204
- Port 3206
- Port 4211
- Port 5220
- Port 6227
- Port 7230
- Port 8237
- Port 9241
- Port 10246
- Port 11250
- Port 12250
- Port 13258
- Port 14260
- Port 15268
- Registers Controlling Port Function270
- Port Function Operations289
- Writing to I/O Port289
- Reading from I/O Port289
- Operations on I/O Port289
- Connecting to External Device with Different Potential (1.8 V, 2.5 V, 3 V)290
- Settings of Port Mode Register, and Output Latch When Using Alternate Function292
- Cautions When Using Port Function298
- Cautions on 1-Bit Manipulation Instruction for Port Register N (Pn)298
- Cautions on the Pin Settings on the Products Other than 128-Pin299
Chapter 5 Clock Generator301
- Functions of Clock Generator301
- Configuration of Clock Generator303
- Registers Controlling Clock Generator305
- System Clock Oscillator321
- X1 Oscillator321
- XT1 Oscillator321
- High-Speed On-Chip Oscillator325
- Low-Speed On-Chip Oscillator325
- Clock Generator Operation326
- Controlling Clock328
- Example of Setting High-Speed On-Chip Oscillator328
- Example of Setting X1 Oscillation Clock329
- Example of Setting XT1 Oscillation Clock330
- CPU Clock Status Transition Diagram331
- Condition before Changing CPU Clock and Processing after Changing CPU Clock337
- Time Required for Switchover of CPU Clock and Main System Clock339
- Conditions before Clock Oscillation Is Stopped340
Chapter 6 Timer Array Unit341
- Functions of Timer Array Unit343
- Independent Channel Operation Function343
- Simultaneous Channel Operation Function344
- 8-Bit Timer Operation Function (Channels 1 and 3 Only)345
- LIN-Bus Supporting Function (Channel 7 of Unit 0 Only)346
- Configuration of Timer Array Unit347
- Registers Controlling Timer Array Unit353
- Basic Rules of Timer Array Unit378
- Basic Rules of Simultaneous Channel Operation Function378
- Basic Rules of 8-Bit Timer Operation Function (Channels 1 and 3 Only)380
- Operation Timing of Counter381
- Count Clock (Ftclk)381
- Start Timing of Counter383
- Channel Output (Tomn Pin) Control389
- Tomn Pin Output Circuit Configuration389
- Tomn Pin Output Setting390
- Cautions on Channel Output Operation391
- Collective Manipulation of Tomn Bit397
- Timer Interrupt and Tomn Pin Output at Operation Start398
- Independent Channel Operation Function of Timer Array Unit399
- Operation as Interval Timer/Square Wave Output399
- Operation as External Event Counter405
- Operation as Frequency Divider (Channel 0 of Unit 0 Only)410
- Operation as Input Pulse Interval Measurement414
- Operation as Input Signal High-/Low-Level Width Measurement418
- Operation as Delay Counter422
- Simultaneous Channel Operation Function of Timer Array Unit427
- Operation as One-Shot Pulse Output Function427
- Operation as PWM Function434
- Operation as Multiple PWM Output Function441
- Cautions When Using Timer Array Unit449
- Cautions When Using Timer Output449
Chapter 7 Real-Time Clock450
- Functions of Real-Time Clock450
- Configuration of Real-Time Clock450
- Registers Controlling Real-Time Clock452
- Real-Time Clock Operation467
- Starting Operation of Real-Time Clock467
- Shifting to STOP Mode after Starting Operation468
- Reading/Writing Real-Time Clock469
- Setting Alarm of Real-Time Clock471
- Hz Output of Real-Time Clock472
- Example of Watch Error Correction of Real-Time Clock473
Chapter 8 Interval Timer476
- Functions of Interval Timer476
- Configuration of Interval Timer476
- Registers Controlling Interval Timer477
- Interval Timer Operation480
Chapter 9 Clock Output/Buzzer Output Controller481
- Functions of Clock Output/Buzzer Output Controller481
- Configuration of Clock Output/Buzzer Output Controller483
- Registers Controlling Clock Output/Buzzer Output Controller483
- Operations of Clock Output/Buzzer Output Controller486
- Operation as Output Pin486
Chapter 10 Watchdog Timer487
- Functions of Watchdog Timer487
- Configuration of Watchdog Timer488
- Register Controlling Watchdog Timer489
- Operation of Watchdog Timer490
- Controlling Operation of Watchdog Timer490
- Setting Overflow Time of Watchdog Timer491
- Setting Window Open Period of Watchdog Timer492
- Setting Watchdog Timer Interval Interrupt493
Chapter 11 A/D Converter494
- Function of A/D Converter494
- Configuration of A/D Converter496
- Registers Used in A/D Converter498
- A/D Converter Conversion Operations523
- Input Voltage and Conversion Results525
- A/D Converter Operation Modes526
- Software Trigger Mode (Select Mode, Sequential Conversion Mode)526
- Software Trigger Mode (Select Mode, One-Shot Conversion Mode)527
- Software Trigger Mode (Scan Mode, Sequential Conversion Mode)528
- Software Trigger Mode (Scan Mode, One-Shot Conversion Mode)529
- Hardware Trigger No-Wait Mode (Select Mode, Sequential Conversion Mode)530
- Hardware Trigger No-Wait Mode (Select Mode, One-Shot Conversion Mode)531
- Hardware Trigger No-Wait Mode (Scan Mode, Sequential Conversion Mode)532
- Hardware Trigger No-Wait Mode (Scan Mode, One-Shot Conversion Mode)533
- Hardware Trigger Wait Mode (Select Mode, Sequential Conversion Mode)534
- Hardware Trigger Wait Mode (Select Mode, One-Shot Conversion Mode)535
- Hardware Trigger Wait Mode (Scan Mode, Sequential Conversion Mode)536
- Hardware Trigger Wait Mode (Scan Mode, One-Shot Conversion Mode)537
- A/D Converter Setup Flowchart538
- Setting up Software Trigger Mode539
- Setting up Hardware Trigger No-Wait Mode540
- Setting up Hardware Trigger Wait Mode541
- Setup When Using Temperature Sensor542
- Mode)542
- Setting up Test Mode543
- SNOOZE Mode Function544
- How to Read A/D Converter Characteristics Table547
- Cautions for A/D Converter549
Chapter 12 Serial Array Unit553
- Functions of Serial Array Unit555
- 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31)555
- UART (UART0 to UART3)556
- Simplified I 2 C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31)557
- Configuration of Serial Array Unit558
- Registers Controlling Serial Array Unit564
- Operation Stop Mode590
- Stopping the Operation by Units591
- Stopping the Operation by Channels592
- Operation of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) Communication593
- Master Transmission596
- Master Reception606
- Master Transmission/Reception615
- Slave Transmission624
- Slave Reception633
- Slave Transmission/Reception640
- SNOOZE Mode Function650
- Calculating Transfer Clock Frequency654
- Procedure for Processing Errors that Occurred During 3-Wire Serial I/O656
- CSI20, CSI21, CSI30, CSI31) Communication656
- Operation of UART (UART0 to UART3) Communication657
- UART Transmission660
- UART Reception670
- SNOOZE Mode Function677
- Calculating Baud Rate682
- Procedure for Processing Errors that Occurred During UART (UART0 to UART3) Communication667686
- LIN Communication Operation687
- LIN Transmission687
- LIN Reception690
- Operation of Simplified I C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31) Communication696
- Address Field Transmission699
- Data Transmission705
- Data Reception709
- Stop Condition Generation714
- Calculating Transfer Rate715
- Procedure for Processing Errors that Occurred During Simplified I C717
- IIC20, IIC21, IIC30, IIC31) Communication717
Chapter 13 Serial Interface Iica718
- Functions of Serial Interface IICA718
- Configuration of Serial Interface IICA721
- Registers Controlling Serial Interface IICA724
- I C Bus Mode Functions738
- Pin Configuration738
- Setting Transfer Clock by Using IICWL0 and IICWH0 Registers739
- I C Bus Definitions and Control Methods741
- Start Conditions741
- Addresses742
- Transfer Direction Specification742
- Acknowledge (ACK)743
- Stop Condition744
- Wait745
- Canceling Wait747
- Interrupt Request (INTIICA0) Generation Timing and Wait Control748
- Address Match Detection Method749
- Error Detection749
- Extension Code749
- Arbitration750
- Wakeup Function752
- Communication Reservation755
- Cautions759
- Communication Operations760
- Timing of I 2 C Interrupt Request (INTIICA0) Occurrence767
- Timing Charts788
Chapter 14 Multiplier and Divider/Multiply-Accumulator803
- Functions of Multiplier and Divider/Multiply-Accumulator803
- Configuration of Multiplier and Divider/Multiply-Accumulator803
- Register Controlling Multiplier and Divider/Multiply-Accumulator809
- Operations of Multiplier and Divider/Multiply-Accumulator811
- Multiplication (Unsigned) Operation811
- Multiplication (Signed) Operation812
- Multiply-Accumulation (Unsigned) Operation813
- Multiply-Accumulation (Signed) Operation815
- Division Operation817
Chapter 15 Dma Controller819
- Functions of DMA Controller819
- Configuration of DMA Controller820
- Registers Controlling DMA Controller823
- Operation of DMA Controller828
- Operation Procedure828
- Transfer Mode829
- Termination of DMA Transfer829
- Example of Setting of DMA Controller830
- CSI Consecutive Transmission830
- Consecutive Capturing of A/D Conversion Results832
- UART Consecutive Reception + ACK Transmission834
- Holding DMA Transfer Pending by Dwaitn Bit836
- Forced Termination by Software837
- Cautions on Using DMA Controller839
Chapter 16 Interrupt Functions841
- Interrupt Function Types841
- Interrupt Sources and Configuration841
- Registers Controlling Interrupt Functions848
- Interrupt Servicing Operations861
- Maskable Interrupt Request Acknowledgment861
- Software Interrupt Request Acknowledgment864
- Multiple Interrupt Servicing864
- Interrupt Request Hold868
Chapter 17 Key Interrupt Function869
- Functions of Key Interrupt869
- Configuration of Key Interrupt869
- Register Controlling Key Interrupt871
Chapter 18 Standby Function872
- Standby Function and Configuration872
- Standby Function872
- Registers Controlling Standby Function873
- Standby Function Operation876
- HALT Mode876
- STOP Mode881
- SNOOZE Mode886
Chapter 19 Reset Function888
- Register for Confirming Reset Source898
Chapter 20 Power-On-Reset Circuit900
- Functions of Power-On-Reset Circuit900
- Configuration of Power-On-Reset Circuit901
- Operation of Power-On-Reset Circuit901
- Cautions for Power-On-Reset Circuit904
Chapter 21 Voltage Detector906
- Functions of Voltage Detector906
- Configuration of Voltage Detector907
- Registers Controlling Voltage Detector907
- Operation of Voltage Detector912
- When Used as Reset Mode912
- When Used as Interrupt Mode914
- When Used as Interrupt and Reset Mode916
- Cautions for Voltage Detector919
Chapter 22 Safety Functions921
- Overview of Safety Functions921
- Registers Used by Safety Functions922
- Operation of Safety Functions922
- Flash Memory CRC Operation Function (High-Speed CRC)922
- CRC Operation Function (General-Purpose CRC)926
- RAM Parity Error Detection Function928
- RAM Guard Function929
- SFR Guard Function930
- Invalid Memory Access Detection Function931
- Frequency Detection Function933
- A/D Test Function935
Chapter 23 Regulator939
- Regulator Overview939
Chapter 24 Option Byte940
- Functions of Option Bytes940
- User Option Byte (000C0H to 000C2H/010C0H to 010C2H)940
- On-Chip Debug Option Byte (000C3H/ 010C3H)941
- Format of User Option Byte942
- Format of On-Chip Debug Option Byte946
- Setting of Option Byte947
Chapter 25 Flash Memory948
- Writing to Flash Memory by Using Flash Memory Programmer949
- Programming Environment951
- Communication Mode951
- Writing to Flash Memory by Using External Device (that Incorporates UART)952
- Programming Environment952
- Communication Mode953
- Connection of Pins on Board954
- P40/TOOL0 Pin954
- RESET Pin954
- Port Pins955
- REGC Pin955
- X1 and X2 Pins955
- Power Supply955
- Data Flash956
- Data Flash Overview956
- Register Controlling Data Flash Memory957
- Procedure for Accessing Data Flash Memory958
- Programming Method959
- Controlling Flash Memory959
- Flash Memory Programming Mode960
- Selecting Communication Mode961
- Communication Commands962
- Description of Signature Data963
- Security Settings964
- Flash Memory Programming by Self-Programming966
- Boot Swap Function968
- Flash Shield Window Function970
Chapter 26 On-Chip Debug Function971
- Connecting E1 On-Chip Debugging Emulator to RL78/G13971
- On-Chip Debug Security ID972
- Securing of User Resources972
Chapter 27 Bcd Correction Circuit974
- BCD Correction Circuit Function974
- Registers Used by BCD Correction Circuit974
- BCD Correction Circuit Operation975
Chapter 28 Instruction Set977
- Conventions Used in Operation List978
- Operand Identifiers and Specification Methods978
- Description of Operation Column979
- Description of Flag Operation Column980
- PREFIX Instruction980
- Operation List981
Chapter 29 Electrical Specifications998
- Pins Mounted According to Product998
- Port Functions998
- Non-Port Functions998
- Absolute Maximum Ratings999
- Oscillator Characteristics1001
- Main System Clock Oscillator Characteristics1001
- On-Chip Oscillator Characteristics1002
- Subsystem Clock Oscillator Characteristics1003
- Recommended Oscillator Constants1004
- DC Characteristics1007
- Pin Characteristics1007
- Supply Current Characteristics1012
- AC Characteristics1025
- Basic Operation1025
- Peripheral Functions Characteristics1027
- Serial Array Unit1027
- Serial Interface IICA1050
- On-Chip Debug (UART)1051
- Analog Characteristics1051
- A/D Converter Characteristics1051
- Temperature Sensor Characteristics1055
- POR Circuit Characteristics1055
- LVD Circuit Characteristics1056
- Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics1059
- Flash Memory Programming Characteristics1059
- Timing Specs for Switching Modes1060
Chapter 30 Package Drawings1061
- 20-Pin Products1061
- 24-Pin Products1062
- 25-Pin Products1063
- 30-Pin Products1064
- 32-Pin Products1065
- 36-Pin Products1066
- 40-Pin Products1067
- 44-Pin Products1068
- 48-Pin Products1069
- 52-Pin Products1071
- 64-Pin Products1072
- 80-Pin Products1076
- 100-Pin Products1078
- 128-Pin Products1080
Appendix A Revision History1081
- Major Revisions in this Edition1081
- Revision History of Preceding Editions1088

Renesas RL78/G13 - Chapter 3 Cpu Architecture; Memory Space

Table of Contents

Other manuals for Renesas RL78/G13

Related product manuals