RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA
R01UH0146EJ0100 Rev.1.00 769
Sep 22, 2011
13.6 Timing Charts
When using the I
2
C bus mode, the master device outputs an address via the serial bus to select one of several slave
devices as its communication partner.
After outputting the slave address, the master device transmits the TRC0 bit (bit 3 of the IICA status register 0 (IICS0)),
which specifies the data transfer direction, and then starts serial communication with the slave device.
Figures 13-32 and 13-33 show timing charts of the data communication.
The IICA shift register 0 (IICA0)’s shift operation is synchronized with the falling edge of the serial clock (SCLA0). The
transmit data is transferred to the SO latch and is output (MSB first) via the SDAA0 pin.
Data input via the SDAA0 pin is captured into IICA0 at the rising edge of SCLA0.
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