Renesas RL78/G13

RL78/G13 CHAPTER 5 CLOCK GENERATOR
R01UH0146EJ0100 Rev.1.00 286
Sep 22, 2011
Remark fX: X1 clock oscillation frequency
fIH: High-speed on-chip oscillator clock frequency
f
EX: External main system clock frequency
f
MX: High-speed system clock frequency
fMAIN: Main system clock frequency
f
XT: XT1 clock oscillation frequency
f
EXS: External subsystem clock frequency
fSUB: Subsystem clock frequency
f
CLK: CPU/peripheral hardware clock frequency
f
IL: Low-speed on-chip oscillator clock frequency
5.3 Registers Controlling Clock Generator
The following nine registers are used to control the clock generator.
• Clock operation mode control register (CMC)
• System clock control register (CKC)
• Clock operation status control register (CSC)
• Oscillation stabilization time counter status register (OSTC)
• Oscillation stabilization time select register (OSTS)
• Peripheral enable register 0 (PER0)
• Operation speed mode control register (OSMC)
• High-speed on-chip oscillator frequency select register (HOCODIV)
• High-speed on-chip oscillator trimming register (HIOTRM)
(1) Clock operation mode control register (CMC)
This register is used to set the operation mode of the X1/P121, X2/EXCLK/P122, XT1/P123, and XT2/EXCLKS/P124
pins, and to select a gain of the oscillator.
The CMC register can be written only once by an 8-bit memory manipulation instruction after reset release. This
register can be read by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.