RL78/G13 CHAPTER 21 VOLTAGE DETECTOR
R01UH0146EJ0100 Rev.1.00 896
Sep 22, 2011
Figure 21-5. Timing of Voltage Detector Internal Interrupt Signal Generation
(Option Byte LVIMDS1, LVIMDS0 = 0, 1)
Internal reset signal
Supply voltage (V
DD
)
LVIMK flag
(set by software)
Time
Cleared
LVD reset signal
Cleared by
software
POR reset signal
Note 2
LVIOMSK flag
LVIRF flag
LVIF flag
LVISEN flag
LVIMD flag
V
LVI
V
POR
= 1.51 V (TYP.)
V
PDR
= 1.50 V (TYP.)
L
H
LVILV flag
INTLVI
LVIIF flag
H
Note 1
Cleared by
software
Notes 1. The LVIMK flag is set to “1” by reset signal generation.
2. LVIRF flag is bit 0 of the reset control flag register (RESF).
The LVIRF flag may become 1 from the beginning due to the power-on waveform.
For details of the RESF register, see CHAPTER 19 RESET FUNCTION.
Remark V
POR: POR power supply rise detection voltage
V
PDR: POR power supply fall detection voltage
<R>
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