RL78/G13 CHAPTER 3 CPU ARCHITECTURE
R01UH0146EJ0100 Rev.1.00 128
Sep 22, 2011
Figure 3-19. Correspondence Between Data Memory and Addressing
(R5F100xJ, R5F101xJ (x = F, G, J, L, M, P, S))
Special function register (SFR)
256 bytes
General-purpose register
32 bytes
Code flash memory
256 KB
Special function register (2nd SFR)
2 KB
Mirror
31.75 KB
Reserved
Reserved
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
Short direct
addressing
SFR addressing
Register addressing
00000H
3FFFFH
40000H
EFFFFH
F0000H
F07FFH
F0800H
F0FFFH
F1000H
FAEFFH
FAF00H
FFE1FH
FFE20H
FFEDFH
FFEE0H
FFEFFH
FFF00H
FFF1FH
FFF20H
FFFFFH
RAM
Note 1
20 KB
Data flash memory
Note 2
8 KB
F2FFFH
F3000H
Notes 1. Use of the area FAF00H to FB309H is prohibited when using the self-programming function and data flash
function, because this area is used for self-programming library (R5F100xJ, R5F101xJ (x = F, G, J, L, M, P)
only).
2. R5F100xJ only.
Caution When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS
= 1), be sure to initialize the used RAM area + 10 bytes.
<R>
To Next Page
Loading...
Need help?
General
