Renesas RL78/G13 - Page 169

RL78/G13 CHAPTER 3 CPU ARCHITECTURE
R01UH0146EJ0100 Rev.1.00 150
Sep 22, 2011
Table 3-6. Extended SFR (2nd SFR) List (8/8)
Manipulable Bit Range Address Special Function Register (SFR) Name Symbol R/W
1-bit 8-bit 16-bit
After Reset
F01F4H TT1L
√ √
F01F5H
Timer channel stop register 1
−
TT1 R/W
− −
√
0000H
F01F6H
F01F7H
Timer clock select register 1 TPS1 R/W
− − √
0000H
F01F8H TO1L
− √
F01F9H
Timer output register 1
−
TO1 R/W
− −
√
0000H
F01FAH TOE1L
√ √
F01FBH
Timer output enable register 1
−
TOE1 R/W
− −
√
0000H
F01FCH TOL1L
− √
F01FDH
Timer output level register 1
−
TOL1 R/W
− −
√
0000H
F01FEH TOM1L
− √
F01FFH
Timer output mode register 1
−
TOM1 R/W
− −
√
0000H
F0200H DMA SFR address register 2 DSA2 R/W
− √ −
00H
F0201H DMA SFR address register 3 DSA3 R/W
− √ −
00H
F0202H DMA RAM address register 2L DRA2L R/W
− √
00H
F0203H DMA RAM address register 2H DRA2H
DRA2
R/W
− √
√
00H
F0204H DMA RAM address register 3L DRA3L R/W
− √
00H
F0205H DMA RAM address register 3H DRA3H
DRA3
R/W
− √
√
00H
F0206H DMA byte count register 2L DBC2L R/W
− √
00H
F0207H DMA byte count register 2H DBC2H
DBC2
R/W
− √
√
00H
F0208H DMA byte count register 3L DBC3L R/W
− √
00H
F0209H DMA byte count register 3H DBC3H
DBC3
R/W
− √
√
00H
F020AH DMA mode control register 2 DMC2 R/W
√ √ −
00H
F020BH DMA mode control register 3 DMC3 R/W
√ √ −
00H
F020CH DMA operation control register 2 DRC2 R/W
√ √ −
00H
F020DH DMA operation control register 3 DRC3 R/W
√ √ −
00H
F0230H IICA control register 00 IICCTL00 R/W
√ √ −
00H
F0231H IICA control register 01 IICCTL01 R/W
√ √ −
00H
F0232H IICA low-level width setting
register 0
IICWL0 R/W
− √ −
FFH
F0233H IICA high-level width setting
register 0
IICWH0 R/W
− √ −
FFH
F0234H Slave address register 0 SVA0 R/W
− √ −
00H
F0238H IICA control register 10 IICCTL10 R/W
√ √ −
00H
F0239H IICA control register 11 IICCTL11 R/W
√ √ −
00H
F023AH IICA low-level width setting
register 1
IICWL1 R/W
− √ −
FFH
F023BH IICA high-level width setting
register 1
IICWH1 R/W
− √ −
FFH
F023CH Slave address register 1 SVA1 R/W
− √ −
00H
F02F0H Flash memory CRC control
register
CRC0CTL R/W
√ √ −
00H
F02F2H Flash memory CRC operation
result register
PGCRCL R/W
− − √
0000H
F02FAH CRC data register CRCD R/W
− − √
0000H
Remark For SFRs in the SFR area, see Table 3-5 SFR List.