Renesas RL78/G13 - Page 317

RL78/G13 CHAPTER 5 CLOCK GENERATOR
R01UH0146EJ0100 Rev.1.00 298
Sep 22, 2011
Figure 5-7. Format of Peripheral Enable Register 0 (PER0) (3/3)
Address: F00F0H After reset: 00H R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PER0 RTCEN
IICA1EN
Note 1
ADCEN
IICA0EN
Note 2
SAU1EN
Note 3
SAU0EN
TAU1EN
Note 1
TAU0EN
TAU1EN Control of timer array unit 1 input clock supply
0
Stops input clock supply.
• SFR used by timer array unit 1 cannot be written.
• Timer array unit 1 is in the reset status.
1
Enables input clock supply.
• SFR used by timer array unit 1 can be read and written.
TAU0EN Control of timer array unit 0 input clock supply
0
Stops input clock supply.
• SFR used by timer array unit 0 cannot be written.
• Timer array unit 0 is in the reset status.
1
Enables input clock supply.
• SFR used by timer array unit 0 can be read and written.
Notes 1. 80, 100, and 128-pin products only.
2. This is not provided in the 20-pin products.
3. This is not provided in the 20, 24, and 25-pin products.
Caution Be sure to clear the following bits to 0.
20-pin products: bits 1, 3, 4, 6
24, 25-pin products: bits 1, 3, 6
30, 32, 36, 40, 44, 48, 52, 64-pin products: bits 1, 6