RL78/G13 CHAPTER 5 CLOCK GENERATOR
R01UH0146EJ0100 Rev.1.00 315
Sep 22, 2011
Table 5-3. CPU Clock Transition and SFR Register Setting Examples (3/5)
(6) CPU clock changing from high-speed system clock (C) to high-speed on-chip oscillator clock (B)
(Setting sequence of SFR registers)
CSC Register CKC Register
Setting Flag of SFR Register
Status Transition
HIOSTOP
Oscillation accuracy
stabilization time
MCM0
(C) → (B) 0 30
μ
s 0
Unnecessary if the CPU is operating with the
high-speed on-chip oscillator clock
(7) CPU clock changing from high-speed system clock (C) to subsystem clock (D)
(Setting sequence of SFR registers)
CSC Register CKC Register
Setting Flag of SFR Register
Status Transition
XTSTOP
Waiting for Oscillation
Stabilization
CSS
(C) → (D) 0 Necessary 1
Unnecessary if the CPU is operating with the
subsystem clock
(8) CPU clock changing from subsystem clock (D) to high-speed on-chip oscillator clock (B)
(Setting sequence of SFR registers)
CSC Register CKC Register
Setting Flag of SFR Register
Status Transition
HIOSTOP CSS MCM0
(D) → (B) 0 0 0
Unnecessary if the CPU
is operating with the
high-speed on-chip
oscillator clock
Unnecessary if this
register is already set
Remark (A) to (J) in Table 5-3 correspond to (A) to (J) in Figure 5-15.
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