RL78/G13 CHAPTER 6 TIMER ARRAY UNIT
R01UH0146EJ0100 Rev.1.00 404
Sep 22, 2011
Figure 6-58. Example of Basic Timing of Operation as Delay Counter
TEmn
TDRmn
TCRmn
INTTMmn
ab
0000H
a+1
b+1
FFFFH
TImn
TSmn
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
2. TSmn: Bit n of timer channel start register m (TSm)
TEmn: Bit n of timer channel enable status register m (TEm)
TImn: TImn pin input signal
TCRmn: Timer count register mn (TCRmn)
TDRmn: Timer data register mn (TDRmn)
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