RL78/G13 CHAPTER 8 INTERVAL TIMER
R01UH0146EJ0100 Rev.1.00 459
Sep 22, 2011
(2) Operation speed mode control register (OSMC)
The WUTMMCK0 bit can be used to select the interval timer operation clock.
In addition, by stopping clock functions that are unnecessary, the RTCLPC bit can be used to reduce power
consumption. For details about setting the RTCLPC bit, see CHAPTER 5 CLOCK GENERATOR.
The OSMC register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 8-3. Format of Operation Speed Mode Control Register (OSMC)
Address: F00F3H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
OSMC RTCLPC 0 0
WUTMMCK0
0 0 0 0
WUTMMCK0
Selection of operation clock for real-time clock and interval timer.
0 Subsystem clock (fSUB)
1 Low-speed on-chip oscillator clock (fIL)
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