Renesas RL78/G13 - Page 700

RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0146EJ0100 Rev.1.00 681
Sep 22, 2011
(1) Register setting
Figure 12-105. Example of Contents of Registers for Address Field Transmission of Simplified I
2
C (IIC00, IIC01,
IIC10, IIC11, IIC20, IIC21, IIC30, IIC31) (1/2)
(a) Serial mode register mn (SMRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMRmn
CKSmn
0/1
CCSmn
0 0 0 0 0 0
STSmn
0 0
SISmn0
0 1 0 0
MDmn2
1
MDmn1
0
MDmn0
0
Operation clock (fMCK) of channel n
0: Prescaler output clock CKm0 set by the SPSm register
1: Prescaler output clock CKm1 set by the SPSm register
Operation mode of channel n
0: Transfer end interrupt
(b) Serial communication operation setting register mn (SCRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCRmn
TXEmn
1
RXEmn
0
DAPmn
0
CKPmn
0 0
EOCmn
0
PTCmn1
0
PTCmn0
0
DIRmn
0 0
SLCmn1
0
SLCmn0
1 0 1
DLSmn1
1
DLSmn0
1
Setting of parity bit
00B: No parity
Setting of stop bit
01B: Appending 1 bit (ACK)
(c) Serial data register mn (SDRmn) (lower 8 bits: SIOr)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn
Baud rate setting
0
Transmit data setting (address + R/W)
(d) Serial output register m (SOm)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOm
0 0 0 0
CKOm3
0/1
CKOm2
0/1
CKOm1
0/1
CKOm0
0/1 0 0 0 0
SOm3
0/1
SOm2
0/1
SOm1
0/1
SOm0
0/1
Start condition is generated by manipulating the SOmn bit.
(e) Serial output enable register m (SOEm)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOEm
0 0 0 0 0 0 0 0 0 0 0 0
SOEm3
0/1
SOEm2
0/1
SOEm1
0/1
SOEm0
0/1
SOEmn = 0 until the start condition is generated, and SOEmn =
1 after generation.
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), r: IIC number (r = 00, 01, 10, 11, 20, 21,
30, 31), mn = 00 to 03, 10 to 13
2. : Setting is fixed in the IIC mode, : Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
SIOr