Renesas RL78/G13 - Page 762

RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA
R01UH0146EJ0100 Rev.1.00 743
Sep 22, 2011
(2) Master operation in multi-master system
Figure 13-29. Master Operation in Multi-Master System (1/3)
IICWL0, IICWH0 ← XXH
IICF0 ← 0XH
Setting STCEN0 and IICRSV0
Setting port
SPT0 = 1
SVA0 ← XXH
SPIE0 = 1
START
Slave operation
Slave operation
Releases the bus for a specific period.
Bus status is
being checked.
Yes
Checking bus status
Note
Master operation
starts?
Enables reserving
communication.
Disables reserving
communication.
SPD0 = 1?
STCEN0 = 1?
IICRSV0 = 0?
A
Selects a transfer clock.
Sets a local address.
Sets a start condition.
(Communication start request)
(No communication start request)
• Waiting to be specified as a slave by other master
• Waiting for a communication start request (depends on user program)
Prepares for starting
communication
(generates a stop condition).
Waits for detection
of the stop condition.
No
Yes
Yes
No
INTIICA0
interrupt occurs?
INTIICA0
interrupt occurs?
Yes
No
Yes
No
SPD0 = 1?
Yes
No
Slave operation
No
INTIICA0
interrupt occurs?
Yes
No
1
B
SPIE0 = 0
Yes
No
Waits for a communication request.
Waits for a communication Initial setting
IICCTL00 ← 1XX111XXB
IICE0 = 1
IICCTL00 ← 0XX111XXB
ACKE0 = WTIM0 = SPIE0 = 1
Setting of the port used alternatively as the pin to be used.
First, set the port to input mode and the output latch to 0 (see 13.3 (8) Port mode register 6 (PM6)).
Setting port
Set the port from input mode to output mode and enable the output of the I
2
C bus
(see 13.3 (8) Port mode register 6 (PM6)).
Note Confirm that the bus is released (CLD0 bit = 1, DAD0 bit = 1) for a specific period (for example, for a period of
one frame). If the SDAA0 pin is constantly at low level, decide whether to release the I
2
C bus (SCLA0 and
SDAA0 pins = high level) in conformance with the specifications of the product that is communicating.