Renesas RL78/G13 User Manual

RL78/G13 CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR
R01UH0146EJ0100 Rev.1.00 791
Sep 22, 2011
Note The DIVST bit can only be set (1) in the division mode. In the division mode, division operation is started by
setting (1) the DIVST bit. The DIVST bit is automatically cleared (0) when the operation ends. In the
multiplication mode, operation is automatically started by setting the multiplier and multiplicand to
multiplication/division data register A (MDAH, MDAL), respectively.
Cautions 1. Do not rewrite the DIVMODE, MDSM bits during operation processing (while the DIVST bit is
1). If it is rewritten, the operation result will be an undefined value.
2. The DIVST bit cannot be cleared (0) by using software during division operation processing
(while the DIVST bit is 1).

Renesas RL78/G13 Specifications

General

Core	RL78
Architecture	16-bit
CPU Speed	32 MHz
Operating Voltage	1.6 V to 5.5 V
Operating Temperature	-40°C to +85°C
Low Power Consumption	Yes
Timers	Multiple 16-bit timers
ADC	10-bit
Communication Interfaces	UART, I2C
Package Options	LQFP, QFN
DMA Channels	Available
D/A Converter	No