RL78/G13 CHAPTER 28 INSTRUCTION SET
R01UH0146EJ0100 Rev.1.00 978
Sep 22, 2011
Table 28-5. Operation List (17/17)
Notes 1. Number of CPU clocks (f
CLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or
when no data is accessed.
2. Number of CPU clocks (f
CLK) when the program memory area is accessed.
3. This indicates the number of clocks “when condition is not met/when condition is met”.
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction
from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
Clocks Flag
Instruction
Group
Mnemonic Operands Bytes
Note 1 Note 2
Clocks
Z AC CY
saddr.bit, $addr20 4 3/5
Note3
−
PC ← PC + 4 + jdisp8 if (saddr).bit = 0
sfr.bit, $addr20 4 3/5
Note3
−
PC ← PC + 4 + jdisp8 if sfr.bit = 0
A.bit, $addr20 3 3/5
Note3
−
PC ← PC + 3 + jdisp8 if A.bit = 0
PSW.bit, $addr20 4 3/5
Note3
−
PC ← PC + 4 + jdisp8 if PSW.bit = 0
[HL].bit, $addr20 3 3/5
Note3
6/7 PC ← PC + 3 + jdisp8 if (HL).bit = 0
BF
ES:[HL].bit,
$addr20
4 4/6
Note3
7/8 PC ← PC + 4 + jdisp8 if (ES, HL).bit = 0
saddr.bit, $addr20 4 3/5
Note3
−
PC ← PC + 4 + jdisp8 if (saddr).bit = 1
then reset (saddr).bit
sfr.bit, $addr20 4 3/5
Note3
−
PC ← PC + 4 + jdisp8 if sfr.bit = 1
then reset sfr.bit
A.bit, $addr20 3 3/5
Note3
−
PC ← PC + 3 + jdisp8 if A.bit = 1
then reset A.bit
PSW.bit, $addr20 4 3/5
Note3
−
PC ← PC + 4 + jdisp8 if PSW.bit = 1
then reset PSW.bit
× × ×
[HL].bit, $addr20 3 3/5
Note3
−
PC ← PC + 3 + jdisp8 if (HL).bit = 1
then reset (HL).bit
Condition
al branch
BTCLR
ES:[HL].bit,
$addr20
4 4/6
Note3
−
PC ← PC + 4 + jdisp8 if (ES, HL).bit = 1
then reset (ES, HL).bit
SKC
−
2 1
−
Next instruction skip if CY = 1
SKNC
−
2 1
−
Next instruction skip if CY = 0
SKZ
−
2 1
−
Next instruction skip if Z = 1
SKNZ
−
2 1
−
Next instruction skip if Z = 0
SKH
−
2 1
−
Next instruction skip if (Z∨CY)=0
Conditional
skip
SKNH
−
2 1
−
Next instruction skip if (Z∨CY)=1
SEL
Note4
RBn 2 1
−
RBS[1:0] ← n
NOP
−
1 1
−
No Operation
EI
−
3 4
−
IE ← 1 (Enable Interrupt)
DI
−
3 4
−
IE ← 0 (Disable Interrupt)
HALT
−
2 3
−
Set HALT Mode
CPU
control
STOP
−
2 3
−
Set STOP Mode
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