Siemens CPU 410-5H Process Automation - Reproducibility of Delay and Watchdog Interrupts

Supplementary information
16.15 Cycle and response times of the CPU 410-5H
CPU 410-5H Process Automation/CPU 410 SMART
System Manual, 10/2013, A5E32631667-AA
291
● Hardware interrupt response time of SM 421; DI 16×UC 24/60 V:
– Internal interrupt processing time: 0.5 ms
– Input delay: 0.5 ms
● The DP cycle time on the PROFIBUS DP is irrelevant, because the signal modules are
installed in the central controller.
The hardware interrupt response time is equivalent to the sum of the listed time factors:
Hardware interrupt response time = 0.3 ms + 0.3 ms + 0.5 ms + 0.5 ms =
approx. 1.6 ms
.
This calculated hardware interrupt response time is the time between detection of a signal at
the digital input and the call of the first instruction in OB 4x.
16.15.9
Reproducibility of delay and watchdog interrupts
Definition of "reproducibility"
Time-delay interrupt:
The period that expires between the call of the first operation in the interrupt OB and the
programmed time of interrupt.
Cyclic interrupt:
The fluctuation range of the interval between two successive calls, measured between the
respective initial operations of the interrupt OB.
Reproducibility
The following table contains the reproducibility of time-delay and cyclic interrupts of the
CPUs.
Table 16- 20 Reproducibility of time-delay and cyclic interrupts of the CPUs
Module
Reproducibility
Time-delay interrupt
Cyclic interrupt
CPU 410-5H stand-alone mode
± 120 µs
± 160 µs
CPU 410-5H redundant
± 200 µs
± 180 µs
These times only apply if the interrupt can actually be executed at this time and if it is not
delayed, for example, by higher-priority interrupts or queued interrupts of equal priority.