Supplementary information
16.15 Cycle and response times of the CPU 410-5H
CPU 410-5H Process Automation/CPU 410 SMART
288 System Manual, 10/2013, A5E32631667-AA
Calculating the longest response time
● Longest response time
22.5 ms * 2
.
● Delay of inputs and outputs
– The maximum input delay of the digital input module SM 421; DI 32×DC 24 V is 4.8
ms per channel
– The output delay of the digital output module SM 422; DO 16×DC 24 V/2A is
negligible.
– An interference frequency suppression of 50 Hz was assigned for the analog input
module SM 431; AI 8×13Bit. The result is a conversion time of 25 ms per channel. As
8 channels are active, a cycle time of the analog input module of 200 ms results.
– Analog output module SM 432; AO 8×13Bit was assigned for measuring range 0 ... 10
V. This results in a conversion time of 0.3 ms per channel. Since 8 channels are
active, the result is a cycle time of 2.4 ms. The transient time for a resistive load of 0.1
ms must be added to this. The result is an analog output response time of 2.5 ms.
● All components are installed in the central controller, so DP cycle times can be ignored.
● Case 1: The system sets an output channel of the digital output module after a digital
input signal is read in. The result is as follows:
Response time = 45 ms + 4.8 ms = 49.8 ms.
● Case 2: The system reads in and outputs an analog value. The result is as follows:
Response time = 45 ms + 200 ms + 2.5 ms = 247.5 ms.
Interrupt response time
Definition of interrupt response time
The interrupt response time is the time from the first occurrence of an interrupt signal to the
call of the first instruction in the interrupt OB.
General rule: Higher priority interrupts are handled first. This means the interrupt response
time is increased by the program execution time of the higher-priority interrupt OBs, and by
previous interrupt OBs of the same priority which have not yet been processed (queue).
Note that any update of the standby CPU extends the interrupt response time.