Program instructions
7.6 Counters
S7-200 SMART
276 System Manual, V2.3, 07/2017, A5E03822230-AF
A status byte for each high-speed counter provides status memory bits that indicate the
current counting direction and whether the current value is greater than or equal to the
preset value. The following table defines these status bits for each high-speed counter.
Note
Status bits are valid only wh
ile the high-speed counter interrupt routine executes. The
purpose of monitoring the state of the high
-speed counter is to enable interrupts for the
events that are of consequence to the operation being performed.
Table 7- 14 Status bits for HSC0, HSC1, HSC2, HSC3, HSC4, and HSC5
SM36.5 SM46.5 SM56.5 SM136.5
SM146.5 SM156.5
Current counting direction status bit:
• 0 = Counting down
• 1 = Counting up
SM36.6 SM46.6 SM56.6 SM136.6
SM146.6 SM156.6
Current value equals preset value
status bit:
• 0 = Not equal
• 1 = Equal
SM36.7 SM46.7 SM56.7 SM136.7
SM146.7 SM156.7
Current value greater than preset
value status bit:
• 0 = Less than or equal
• 1 = Greater than
Refer to the following sections for further information:
● High-speed counter instructions (Page 257)
● High-speed counter summary (Page 260)
● Example initialization sequences for high-speed counters (Page 277)
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